Search

An T. Luu

Examiner (ID: 5797, Phone: (571)272-1746 , Office: P/2842 )

Most Active Art Unit
2816
Art Unit(s)
2502, 2816, 2842
Total Applications
2105
Issued Applications
1967
Pending Applications
23
Abandoned Applications
118

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6241580 [patent_doc_number] => 20100134169 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-03 [patent_title] => 'Delay Circuit' [patent_app_type] => utility [patent_app_number] => 12/591726 [patent_app_country] => US [patent_app_date] => 2009-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8947 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0134/20100134169.pdf [firstpage_image] =>[orig_patent_app_number] => 12591726 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/591726
Delay circuit Nov 29, 2009 Issued
Array ( [id] => 4601154 [patent_doc_number] => 07977990 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-12 [patent_title] => 'Duty correction circuit, duty correction system, and duty correction method' [patent_app_type] => utility [patent_app_number] => 12/626315 [patent_app_country] => US [patent_app_date] => 2009-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 21 [patent_no_of_words] => 4429 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/977/07977990.pdf [firstpage_image] =>[orig_patent_app_number] => 12626315 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/626315
Duty correction circuit, duty correction system, and duty correction method Nov 24, 2009 Issued
Array ( [id] => 4444277 [patent_doc_number] => 07928791 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-04-19 [patent_title] => 'Method and apparatus for clock calibration in a clocked digital device' [patent_app_type] => utility [patent_app_number] => 12/624267 [patent_app_country] => US [patent_app_date] => 2009-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 12356 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/928/07928791.pdf [firstpage_image] =>[orig_patent_app_number] => 12624267 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/624267
Method and apparatus for clock calibration in a clocked digital device Nov 22, 2009 Issued
Array ( [id] => 6403983 [patent_doc_number] => 20100148838 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-17 [patent_title] => 'WIDE RANGE DELAY CELL' [patent_app_type] => utility [patent_app_number] => 12/623982 [patent_app_country] => US [patent_app_date] => 2009-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1849 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20100148838.pdf [firstpage_image] =>[orig_patent_app_number] => 12623982 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/623982
Wide range delay cell Nov 22, 2009 Issued
Array ( [id] => 4488885 [patent_doc_number] => 07902893 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-03-08 [patent_title] => 'Clock-signal generator' [patent_app_type] => utility [patent_app_number] => 12/620149 [patent_app_country] => US [patent_app_date] => 2009-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 7844 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/902/07902893.pdf [firstpage_image] =>[orig_patent_app_number] => 12620149 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/620149
Clock-signal generator Nov 16, 2009 Issued
Array ( [id] => 5941435 [patent_doc_number] => 20110102055 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-05 [patent_title] => 'LOW-SIDE DRIVER HIGH-VOLTAGE TRANSIENT PROTECTION CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/613363 [patent_app_country] => US [patent_app_date] => 2009-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2972 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0102/20110102055.pdf [firstpage_image] =>[orig_patent_app_number] => 12613363 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/613363
Low-side driver high-voltage transient protection circuit Nov 4, 2009 Issued
Array ( [id] => 4630051 [patent_doc_number] => 08008953 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-08-30 [patent_title] => 'Gate control circuit' [patent_app_type] => utility [patent_app_number] => 12/590326 [patent_app_country] => US [patent_app_date] => 2009-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 6261 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/008/08008953.pdf [firstpage_image] =>[orig_patent_app_number] => 12590326 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/590326
Gate control circuit Nov 3, 2009 Issued
Array ( [id] => 6306133 [patent_doc_number] => 20100109736 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-06 [patent_title] => 'ELECTRONIC DEVICE AND SQUARE WAVE GENERATOR THEREOF' [patent_app_type] => utility [patent_app_number] => 12/612664 [patent_app_country] => US [patent_app_date] => 2009-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1171 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20100109736.pdf [firstpage_image] =>[orig_patent_app_number] => 12612664 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/612664
Electronic device and square wave generator thereof Nov 3, 2009 Issued
Array ( [id] => 5941418 [patent_doc_number] => 20110102038 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-05 [patent_title] => 'DUTY RATIO CONTROL APPARATUS AND DUTY RATIO CONTROL METHOD' [patent_app_type] => utility [patent_app_number] => 12/611381 [patent_app_country] => US [patent_app_date] => 2009-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5504 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0102/20110102038.pdf [firstpage_image] =>[orig_patent_app_number] => 12611381 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/611381
Duty ratio control apparatus and duty ratio control method Nov 2, 2009 Issued
Array ( [id] => 6241566 [patent_doc_number] => 20100134162 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-03 [patent_title] => 'CLOCK SIGNAL GENERATION CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/606666 [patent_app_country] => US [patent_app_date] => 2009-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5079 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0134/20100134162.pdf [firstpage_image] =>[orig_patent_app_number] => 12606666 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/606666
Clock signal generation circuit Oct 26, 2009 Issued
Array ( [id] => 4533920 [patent_doc_number] => 07924077 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-04-12 [patent_title] => 'Signal processing apparatus including latch circuit' [patent_app_type] => utility [patent_app_number] => 12/605626 [patent_app_country] => US [patent_app_date] => 2009-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4960 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/924/07924077.pdf [firstpage_image] =>[orig_patent_app_number] => 12605626 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/605626
Signal processing apparatus including latch circuit Oct 25, 2009 Issued
Array ( [id] => 4640232 [patent_doc_number] => 08018260 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-09-13 [patent_title] => 'Compensation of degradation of performance of semiconductor devices by clock duty cycle adaptation' [patent_app_type] => utility [patent_app_number] => 12/604532 [patent_app_country] => US [patent_app_date] => 2009-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 7751 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/018/08018260.pdf [firstpage_image] =>[orig_patent_app_number] => 12604532 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/604532
Compensation of degradation of performance of semiconductor devices by clock duty cycle adaptation Oct 22, 2009 Issued
Array ( [id] => 4544475 [patent_doc_number] => 07876132 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-01-25 [patent_title] => 'Floating well circuit operable in a failsafe condition and a tolerant condition' [patent_app_type] => utility [patent_app_number] => 12/580280 [patent_app_country] => US [patent_app_date] => 2009-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5691 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/876/07876132.pdf [firstpage_image] =>[orig_patent_app_number] => 12580280 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/580280
Floating well circuit operable in a failsafe condition and a tolerant condition Oct 15, 2009 Issued
Array ( [id] => 8560650 [patent_doc_number] => 08334716 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-12-18 [patent_title] => 'Digital phase detection circuit and method' [patent_app_type] => utility [patent_app_number] => 12/580175 [patent_app_country] => US [patent_app_date] => 2009-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4353 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12580175 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/580175
Digital phase detection circuit and method Oct 14, 2009 Issued
Array ( [id] => 4619873 [patent_doc_number] => 07999594 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-16 [patent_title] => 'Semiconductor integrated circuit and control signal distribution method' [patent_app_type] => utility [patent_app_number] => 12/585962 [patent_app_country] => US [patent_app_date] => 2009-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4499 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/999/07999594.pdf [firstpage_image] =>[orig_patent_app_number] => 12585962 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/585962
Semiconductor integrated circuit and control signal distribution method Sep 28, 2009 Issued
Array ( [id] => 7505475 [patent_doc_number] => 08035436 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-10-11 [patent_title] => 'Passive capacitively injected phase interpolator' [patent_app_type] => utility [patent_app_number] => 12/566506 [patent_app_country] => US [patent_app_date] => 2009-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4621 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/035/08035436.pdf [firstpage_image] =>[orig_patent_app_number] => 12566506 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/566506
Passive capacitively injected phase interpolator Sep 23, 2009 Issued
Array ( [id] => 4614756 [patent_doc_number] => 07990200 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-02 [patent_title] => 'Pulse width modulation control system' [patent_app_type] => utility [patent_app_number] => 12/563148 [patent_app_country] => US [patent_app_date] => 2009-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1500 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/990/07990200.pdf [firstpage_image] =>[orig_patent_app_number] => 12563148 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/563148
Pulse width modulation control system Sep 19, 2009 Issued
Array ( [id] => 6265388 [patent_doc_number] => 20100253409 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-07 [patent_title] => 'CLOCK GENERATION SYSTEM AND CLOCK DIVIDING MODULE' [patent_app_type] => utility [patent_app_number] => 12/561503 [patent_app_country] => US [patent_app_date] => 2009-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3493 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0253/20100253409.pdf [firstpage_image] =>[orig_patent_app_number] => 12561503 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/561503
CLOCK GENERATION SYSTEM AND CLOCK DIVIDING MODULE Sep 16, 2009 Abandoned
Array ( [id] => 6200221 [patent_doc_number] => 20110063007 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-17 [patent_title] => 'DELAY CIRCUIT WITH DELAY EQUAL TO PERCENTAGE OF INPUT PULSE WIDTH' [patent_app_type] => utility [patent_app_number] => 12/560593 [patent_app_country] => US [patent_app_date] => 2009-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7243 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0063/20110063007.pdf [firstpage_image] =>[orig_patent_app_number] => 12560593 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/560593
Delay circuit with delay equal to percentage of input pulse width Sep 15, 2009 Issued
Array ( [id] => 4578516 [patent_doc_number] => 07830192 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-09 [patent_title] => 'Delay circuit and related method thereof' [patent_app_type] => utility [patent_app_number] => 12/553963 [patent_app_country] => US [patent_app_date] => 2009-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4658 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/830/07830192.pdf [firstpage_image] =>[orig_patent_app_number] => 12553963 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/553963
Delay circuit and related method thereof Sep 2, 2009 Issued
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