Search

An T. Luu

Examiner (ID: 5797, Phone: (571)272-1746 , Office: P/2842 )

Most Active Art Unit
2816
Art Unit(s)
2502, 2816, 2842
Total Applications
2105
Issued Applications
1967
Pending Applications
23
Abandoned Applications
118

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4605938 [patent_doc_number] => 07986923 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-07-26 [patent_title] => 'Signal channel balancing' [patent_app_type] => utility [patent_app_number] => 12/313596 [patent_app_country] => US [patent_app_date] => 2008-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2017 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/986/07986923.pdf [firstpage_image] =>[orig_patent_app_number] => 12313596 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/313596
Signal channel balancing Nov 19, 2008 Issued
Array ( [id] => 5480387 [patent_doc_number] => 20090203344 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-13 [patent_title] => 'Methods and systems for stereo noise mitigation' [patent_app_type] => utility [patent_app_number] => 12/313044 [patent_app_country] => US [patent_app_date] => 2008-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3576 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0203/20090203344.pdf [firstpage_image] =>[orig_patent_app_number] => 12313044 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/313044
Methods and systems for stereo noise mitigation Nov 16, 2008 Issued
Array ( [id] => 6540861 [patent_doc_number] => 20100124883 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-20 [patent_title] => 'Integrated air loop antenna and transformer antenna assembly' [patent_app_type] => utility [patent_app_number] => 12/313087 [patent_app_country] => US [patent_app_date] => 2008-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2271 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20100124883.pdf [firstpage_image] =>[orig_patent_app_number] => 12313087 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/313087
Integrated air loop antenna and transformer antenna assembly Nov 16, 2008 Issued
Array ( [id] => 103518 [patent_doc_number] => 07728642 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-06-01 [patent_title] => 'Ripple counter based programmable delay line' [patent_app_type] => utility [patent_app_number] => 12/270102 [patent_app_country] => US [patent_app_date] => 2008-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5042 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/728/07728642.pdf [firstpage_image] =>[orig_patent_app_number] => 12270102 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/270102
Ripple counter based programmable delay line Nov 12, 2008 Issued
Array ( [id] => 5563116 [patent_doc_number] => 20090135968 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-28 [patent_title] => 'PHASE-ERROR REDUCTION CIRCUITRY FOR AN IQ GENERATOR' [patent_app_type] => utility [patent_app_number] => 12/269491 [patent_app_country] => US [patent_app_date] => 2008-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 5701 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0135/20090135968.pdf [firstpage_image] =>[orig_patent_app_number] => 12269491 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/269491
Phase-error reduction circuitry for an IQ generator Nov 11, 2008 Issued
Array ( [id] => 5407869 [patent_doc_number] => 20090121767 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-14 [patent_title] => 'SIGNAL PROCESSING APPARATUS' [patent_app_type] => utility [patent_app_number] => 12/265225 [patent_app_country] => US [patent_app_date] => 2008-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 9514 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0121/20090121767.pdf [firstpage_image] =>[orig_patent_app_number] => 12265225 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/265225
Signal processing apparatus Nov 4, 2008 Issued
Array ( [id] => 6217106 [patent_doc_number] => 20100052759 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-04 [patent_title] => 'PULSE GENERATOR' [patent_app_type] => utility [patent_app_number] => 12/262174 [patent_app_country] => US [patent_app_date] => 2008-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 845 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0052/20100052759.pdf [firstpage_image] =>[orig_patent_app_number] => 12262174 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/262174
Pulse generator Oct 29, 2008 Issued
Array ( [id] => 6339289 [patent_doc_number] => 20100019819 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-28 [patent_title] => 'Delay Circuit' [patent_app_type] => utility [patent_app_number] => 12/252347 [patent_app_country] => US [patent_app_date] => 2008-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3201 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0019/20100019819.pdf [firstpage_image] =>[orig_patent_app_number] => 12252347 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/252347
Delay Circuit Oct 14, 2008 Abandoned
Array ( [id] => 93565 [patent_doc_number] => 07733148 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-08 [patent_title] => 'Temperature independent delay circuits' [patent_app_type] => utility [patent_app_number] => 12/249237 [patent_app_country] => US [patent_app_date] => 2008-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 4721 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/733/07733148.pdf [firstpage_image] =>[orig_patent_app_number] => 12249237 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/249237
Temperature independent delay circuits Oct 9, 2008 Issued
Array ( [id] => 6361686 [patent_doc_number] => 20100079182 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-01 [patent_title] => 'METHOD AND APPARATUS FOR COUNTER-BASED CLOCK SIGNAL ADAPTATION' [patent_app_type] => utility [patent_app_number] => 12/240645 [patent_app_country] => US [patent_app_date] => 2008-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6993 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0079/20100079182.pdf [firstpage_image] =>[orig_patent_app_number] => 12240645 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/240645
Method and apparatus for counter-based clock signal adaptation Sep 28, 2008 Issued
Array ( [id] => 4436310 [patent_doc_number] => 07898306 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-03-01 [patent_title] => 'High bandwidth phase locked loop (PLL) with feedback loop including a frequency divider' [patent_app_type] => utility [patent_app_number] => 12/235507 [patent_app_country] => US [patent_app_date] => 2008-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 4631 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/898/07898306.pdf [firstpage_image] =>[orig_patent_app_number] => 12235507 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/235507
High bandwidth phase locked loop (PLL) with feedback loop including a frequency divider Sep 21, 2008 Issued
Array ( [id] => 174384 [patent_doc_number] => 07659764 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-02-09 [patent_title] => 'Efficient delay elements' [patent_app_type] => utility [patent_app_number] => 12/212314 [patent_app_country] => US [patent_app_date] => 2008-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 8571 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/659/07659764.pdf [firstpage_image] =>[orig_patent_app_number] => 12212314 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/212314
Efficient delay elements Sep 16, 2008 Issued
Array ( [id] => 8538923 [patent_doc_number] => 08314646 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-20 [patent_title] => 'Signal reproducing device' [patent_app_type] => utility [patent_app_number] => 12/920091 [patent_app_country] => US [patent_app_date] => 2008-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2974 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12920091 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/920091
Signal reproducing device Sep 1, 2008 Issued
Array ( [id] => 5320498 [patent_doc_number] => 20090058488 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-05 [patent_title] => 'Delay circuit, semiconductor control circuit, display device, and electronic device' [patent_app_type] => utility [patent_app_number] => 12/222860 [patent_app_country] => US [patent_app_date] => 2008-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 11585 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0058/20090058488.pdf [firstpage_image] =>[orig_patent_app_number] => 12222860 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/222860
Delay circuit, semiconductor control circuit, display device, and electronic device Aug 17, 2008 Issued
Array ( [id] => 7698952 [patent_doc_number] => 20110227638 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-22 [patent_title] => 'Apparatus For Processing Signals' [patent_app_type] => utility [patent_app_number] => 12/671874 [patent_app_country] => US [patent_app_date] => 2008-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6317 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0227/20110227638.pdf [firstpage_image] =>[orig_patent_app_number] => 12671874 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/671874
Apparatus for processing signals Aug 3, 2008 Issued
Array ( [id] => 6248243 [patent_doc_number] => 20100026367 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-04 [patent_title] => 'DOUBLE-BALANCED SINUSOIDAL MIXING PHASE INTERPOLATOR CIRCUIT AND METHOD' [patent_app_type] => utility [patent_app_number] => 12/183563 [patent_app_country] => US [patent_app_date] => 2008-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9271 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20100026367.pdf [firstpage_image] =>[orig_patent_app_number] => 12183563 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/183563
Double-balanced sinusoidal mixing phase interpolator circuit and method Jul 30, 2008 Issued
Array ( [id] => 6339291 [patent_doc_number] => 20100019821 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-28 [patent_title] => 'METHOD FOR GENERATING A OUTPUT CLOCK SIGNAL HAVING A OUTPUT CYCLE AND A DEVICE HAVING A CLOCK SIGNAL GENERATING CAPABILITIES' [patent_app_type] => utility [patent_app_number] => 12/179826 [patent_app_country] => US [patent_app_date] => 2008-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3365 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0019/20100019821.pdf [firstpage_image] =>[orig_patent_app_number] => 12179826 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/179826
Method for generating a output clock signal having a output cycle and a device having a clock signal generating capabilities Jul 24, 2008 Issued
Array ( [id] => 5407868 [patent_doc_number] => 20090121766 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-14 [patent_title] => 'EXTERNALLY ASYNCHRONOUS INTERNALLY CLOCKED SYSTEM' [patent_app_type] => utility [patent_app_number] => 12/177025 [patent_app_country] => US [patent_app_date] => 2008-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4040 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0121/20090121766.pdf [firstpage_image] =>[orig_patent_app_number] => 12177025 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/177025
Externally asynchronous internally clocked system Jul 20, 2008 Issued
Array ( [id] => 5420254 [patent_doc_number] => 20090146709 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-11 [patent_title] => 'DELAY CIRCUIT OF DELAY LOCKED LOOP HAVING SINGLE AND DUAL DELAY LINES AND CONTROL METHOD OF THE SAME' [patent_app_type] => utility [patent_app_number] => 12/172887 [patent_app_country] => US [patent_app_date] => 2008-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3426 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0146/20090146709.pdf [firstpage_image] =>[orig_patent_app_number] => 12172887 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/172887
Delay circuit of delay locked loop having single and dual delay lines and control method of the same Jul 13, 2008 Issued
Array ( [id] => 7776156 [patent_doc_number] => 08120408 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-02-21 [patent_title] => 'Voltage controlled oscillator delay cell and method' [patent_app_type] => utility [patent_app_number] => 12/218404 [patent_app_country] => US [patent_app_date] => 2008-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3746 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/120/08120408.pdf [firstpage_image] =>[orig_patent_app_number] => 12218404 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/218404
Voltage controlled oscillator delay cell and method Jul 13, 2008 Issued
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