
An T. Luu
Examiner (ID: 5797, Phone: (571)272-1746 , Office: P/2842 )
| Most Active Art Unit | 2816 |
| Art Unit(s) | 2502, 2816, 2842 |
| Total Applications | 2105 |
| Issued Applications | 1967 |
| Pending Applications | 23 |
| Abandoned Applications | 118 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 585387
[patent_doc_number] => 07453310
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-11-18
[patent_title] => 'Switching circuit having two MOS-FETS'
[patent_app_type] => utility
[patent_app_number] => 11/500301
[patent_app_country] => US
[patent_app_date] => 2006-08-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 2021
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 202
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/453/07453310.pdf
[firstpage_image] =>[orig_patent_app_number] => 11500301
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/500301 | Switching circuit having two MOS-FETS | Aug 7, 2006 | Issued |
Array
(
[id] => 377540
[patent_doc_number] => 07312642
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2007-12-25
[patent_title] => 'Continuous, wide-range frequency synthesis and phase tracking methods and apparatus'
[patent_app_type] => utility
[patent_app_number] => 11/498958
[patent_app_country] => US
[patent_app_date] => 2006-08-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2405
[patent_no_of_claims] => 37
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/312/07312642.pdf
[firstpage_image] =>[orig_patent_app_number] => 11498958
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/498958 | Continuous, wide-range frequency synthesis and phase tracking methods and apparatus | Aug 1, 2006 | Issued |
Array
(
[id] => 267579
[patent_doc_number] => 07567106
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-07-28
[patent_title] => 'Duty cycle correction circuit, clock generation circuits, semiconductor devices using the same, and method for generating clock signal'
[patent_app_type] => utility
[patent_app_number] => 11/496447
[patent_app_country] => US
[patent_app_date] => 2006-08-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 19
[patent_no_of_words] => 5316
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/567/07567106.pdf
[firstpage_image] =>[orig_patent_app_number] => 11496447
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/496447 | Duty cycle correction circuit, clock generation circuits, semiconductor devices using the same, and method for generating clock signal | Jul 31, 2006 | Issued |
Array
(
[id] => 602982
[patent_doc_number] => 07432746
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-10-07
[patent_title] => 'CMOS buffer with complementary outputs having reduced voltage swing'
[patent_app_type] => utility
[patent_app_number] => 11/495882
[patent_app_country] => US
[patent_app_date] => 2006-07-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 3484
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 263
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/432/07432746.pdf
[firstpage_image] =>[orig_patent_app_number] => 11495882
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/495882 | CMOS buffer with complementary outputs having reduced voltage swing | Jul 30, 2006 | Issued |
Array
(
[id] => 315391
[patent_doc_number] => 07525364
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-04-28
[patent_title] => 'Delay control circuit'
[patent_app_type] => utility
[patent_app_number] => 11/493622
[patent_app_country] => US
[patent_app_date] => 2006-07-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 5235
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 172
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/525/07525364.pdf
[firstpage_image] =>[orig_patent_app_number] => 11493622
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/493622 | Delay control circuit | Jul 26, 2006 | Issued |
Array
(
[id] => 4655315
[patent_doc_number] => 20080024176
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-01-31
[patent_title] => 'Low variation voltage output differential for differential drivers'
[patent_app_type] => utility
[patent_app_number] => 11/494847
[patent_app_country] => US
[patent_app_date] => 2006-07-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4342
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0024/20080024176.pdf
[firstpage_image] =>[orig_patent_app_number] => 11494847
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/494847 | Low variation voltage output differential for differential drivers | Jul 26, 2006 | Issued |
Array
(
[id] => 5049502
[patent_doc_number] => 20070030046
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-02-08
[patent_title] => 'Delay cell using a capacitor displacement current'
[patent_app_type] => utility
[patent_app_number] => 11/492018
[patent_app_country] => US
[patent_app_date] => 2006-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 1990
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0030/20070030046.pdf
[firstpage_image] =>[orig_patent_app_number] => 11492018
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/492018 | Delay cell using a capacitor displacement current | Jul 24, 2006 | Abandoned |
Array
(
[id] => 576205
[patent_doc_number] => 07463081
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-12-09
[patent_title] => 'Internal voltage generator and internal clock generator including the same, and internal voltage generating method thereof'
[patent_app_type] => utility
[patent_app_number] => 11/490241
[patent_app_country] => US
[patent_app_date] => 2006-07-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 9
[patent_no_of_words] => 5370
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/463/07463081.pdf
[firstpage_image] =>[orig_patent_app_number] => 11490241
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/490241 | Internal voltage generator and internal clock generator including the same, and internal voltage generating method thereof | Jul 20, 2006 | Issued |
Array
(
[id] => 865907
[patent_doc_number] => 07368957
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-05-06
[patent_title] => 'Capacitively coupled floating gate driver'
[patent_app_type] => utility
[patent_app_number] => 11/490573
[patent_app_country] => US
[patent_app_date] => 2006-07-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 22
[patent_no_of_words] => 6486
[patent_no_of_claims] => 38
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/368/07368957.pdf
[firstpage_image] =>[orig_patent_app_number] => 11490573
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/490573 | Capacitively coupled floating gate driver | Jul 20, 2006 | Issued |
Array
(
[id] => 5033502
[patent_doc_number] => 20070098041
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-05-03
[patent_title] => 'ON CHIP TEMPERATURE DETECTOR, TEMPERATURE DETECTION METHOD AND REFRESH CONTROL METHOD USING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 11/459312
[patent_app_country] => US
[patent_app_date] => 2006-07-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 11395
[patent_no_of_claims] => 63
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0098/20070098041.pdf
[firstpage_image] =>[orig_patent_app_number] => 11459312
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/459312 | On chip temperature detector, temperature detection method and refresh control method using the same | Jul 20, 2006 | Issued |
Array
(
[id] => 360246
[patent_doc_number] => 07486125
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-02-03
[patent_title] => 'Delay cells and delay line circuits having the same'
[patent_app_type] => utility
[patent_app_number] => 11/484792
[patent_app_country] => US
[patent_app_date] => 2006-07-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 2934
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/486/07486125.pdf
[firstpage_image] =>[orig_patent_app_number] => 11484792
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/484792 | Delay cells and delay line circuits having the same | Jul 10, 2006 | Issued |
Array
(
[id] => 5659567
[patent_doc_number] => 20060250163
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-11-09
[patent_title] => 'Apparatus and method for adjusting clock skew'
[patent_app_type] => utility
[patent_app_number] => 11/483767
[patent_app_country] => US
[patent_app_date] => 2006-07-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 4513
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0250/20060250163.pdf
[firstpage_image] =>[orig_patent_app_number] => 11483767
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/483767 | Apparatus and method for adjusting clock skew | Jul 10, 2006 | Abandoned |
Array
(
[id] => 5659578
[patent_doc_number] => 20060250174
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-11-09
[patent_title] => 'High resolution digital delay circuit for PLL and DLL'
[patent_app_type] => utility
[patent_app_number] => 11/482562
[patent_app_country] => US
[patent_app_date] => 2006-07-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5301
[patent_no_of_claims] => 57
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0250/20060250174.pdf
[firstpage_image] =>[orig_patent_app_number] => 11482562
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/482562 | High resolution digital delay circuit for PLL and DLL | Jul 6, 2006 | Issued |
Array
(
[id] => 311609
[patent_doc_number] => 07528641
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-05-05
[patent_title] => 'Delay circuit having a correction circuit'
[patent_app_type] => utility
[patent_app_number] => 11/476900
[patent_app_country] => US
[patent_app_date] => 2006-06-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 12
[patent_no_of_words] => 9724
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 177
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/528/07528641.pdf
[firstpage_image] =>[orig_patent_app_number] => 11476900
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/476900 | Delay circuit having a correction circuit | Jun 28, 2006 | Issued |
Array
(
[id] => 394477
[patent_doc_number] => 07298178
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2007-11-20
[patent_title] => 'Clock-generator architecture for a programmable-logic-based system on a chip'
[patent_app_type] => utility
[patent_app_number] => 11/427717
[patent_app_country] => US
[patent_app_date] => 2006-06-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 20
[patent_no_of_words] => 15603
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/298/07298178.pdf
[firstpage_image] =>[orig_patent_app_number] => 11427717
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/427717 | Clock-generator architecture for a programmable-logic-based system on a chip | Jun 28, 2006 | Issued |
Array
(
[id] => 422295
[patent_doc_number] => 07274229
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2007-09-25
[patent_title] => 'Coarse tuning for fractional-N synthesizers'
[patent_app_type] => utility
[patent_app_number] => 11/472889
[patent_app_country] => US
[patent_app_date] => 2006-06-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 9
[patent_no_of_words] => 5111
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 47
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/274/07274229.pdf
[firstpage_image] =>[orig_patent_app_number] => 11472889
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/472889 | Coarse tuning for fractional-N synthesizers | Jun 21, 2006 | Issued |
Array
(
[id] => 5240140
[patent_doc_number] => 20070018631
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-01-25
[patent_title] => 'Averaging circuit apparatus, error signal generation system and method of averaging an error signal'
[patent_app_type] => utility
[patent_app_number] => 11/455377
[patent_app_country] => US
[patent_app_date] => 2006-06-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3586
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0018/20070018631.pdf
[firstpage_image] =>[orig_patent_app_number] => 11455377
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/455377 | Averaging circuit apparatus, error signal generation system and method of averaging an error signal | Jun 18, 2006 | Issued |
Array
(
[id] => 14914
[patent_doc_number] => 07808291
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-10-05
[patent_title] => 'Jitter generating circuit'
[patent_app_type] => utility
[patent_app_number] => 11/916247
[patent_app_country] => US
[patent_app_date] => 2006-06-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4839
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 74
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/808/07808291.pdf
[firstpage_image] =>[orig_patent_app_number] => 11916247
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/916247 | Jitter generating circuit | Jun 17, 2006 | Issued |
Array
(
[id] => 4757156
[patent_doc_number] => 20080309381
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-12-18
[patent_title] => 'Device for Controlling a High-Voltage Transistor, in Particular a Mos Transistor of a High-Voltage Radio-Frequency Generator for the Spark Ignition of an Internal Combustion Engine'
[patent_app_type] => utility
[patent_app_number] => 11/994716
[patent_app_country] => US
[patent_app_date] => 2006-05-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2627
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0309/20080309381.pdf
[firstpage_image] =>[orig_patent_app_number] => 11994716
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/994716 | Device for controlling a high-voltage transistor, in particular a MOS transistor of a high-voltage radio-frequency generator for the spark ignition of an internal combustion engine | May 11, 2006 | Issued |
Array
(
[id] => 5730726
[patent_doc_number] => 20060255840
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-11-16
[patent_title] => 'SIGNAL SAMPLING APPARATUS AND METHOD'
[patent_app_type] => utility
[patent_app_number] => 11/382718
[patent_app_country] => US
[patent_app_date] => 2006-05-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 2548
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0255/20060255840.pdf
[firstpage_image] =>[orig_patent_app_number] => 11382718
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/382718 | Signal sampling apparatus and method | May 10, 2006 | Issued |