Search

An T. Luu

Examiner (ID: 5797, Phone: (571)272-1746 , Office: P/2842 )

Most Active Art Unit
2816
Art Unit(s)
2502, 2816, 2842
Total Applications
2105
Issued Applications
1967
Pending Applications
23
Abandoned Applications
118

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 387177 [patent_doc_number] => 07304547 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-12-04 [patent_title] => 'Method and apparatus to improve frequency stability of an integrated circuit oscillator' [patent_app_type] => utility [patent_app_number] => 11/360184 [patent_app_country] => US [patent_app_date] => 2006-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3737 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/304/07304547.pdf [firstpage_image] =>[orig_patent_app_number] => 11360184 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/360184
Method and apparatus to improve frequency stability of an integrated circuit oscillator Feb 22, 2006 Issued
Array ( [id] => 5653373 [patent_doc_number] => 20060139108 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-29 [patent_title] => 'Controlling a voltage controlled oscillator in a bang-bang phase locked loop' [patent_app_type] => utility [patent_app_number] => 11/356514 [patent_app_country] => US [patent_app_date] => 2006-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7009 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0139/20060139108.pdf [firstpage_image] =>[orig_patent_app_number] => 11356514 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/356514
Controlling a voltage controlled oscillator in a bang-bang phase locked loop Feb 16, 2006 Issued
Array ( [id] => 7597116 [patent_doc_number] => 07619462 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-11-17 [patent_title] => 'Unpowered switch and bleeder circuit' [patent_app_type] => utility [patent_app_number] => 11/351342 [patent_app_country] => US [patent_app_date] => 2006-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11797 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/619/07619462.pdf [firstpage_image] =>[orig_patent_app_number] => 11351342 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/351342
Unpowered switch and bleeder circuit Feb 8, 2006 Issued
Array ( [id] => 458337 [patent_doc_number] => 07245166 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-17 [patent_title] => 'Starter circuit' [patent_app_type] => utility [patent_app_number] => 11/332177 [patent_app_country] => US [patent_app_date] => 2006-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2626 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/245/07245166.pdf [firstpage_image] =>[orig_patent_app_number] => 11332177 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/332177
Starter circuit Jan 16, 2006 Issued
Array ( [id] => 398254 [patent_doc_number] => 07295046 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-11-13 [patent_title] => 'Power down detection circuit' [patent_app_type] => utility [patent_app_number] => 11/327990 [patent_app_country] => US [patent_app_date] => 2006-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 2719 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/295/07295046.pdf [firstpage_image] =>[orig_patent_app_number] => 11327990 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/327990
Power down detection circuit Jan 8, 2006 Issued
Array ( [id] => 865914 [patent_doc_number] => 07368964 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-05-06 [patent_title] => 'Delay locked loop in semiconductor memory device and method for generating divided clock therein' [patent_app_type] => utility [patent_app_number] => 11/320847 [patent_app_country] => US [patent_app_date] => 2005-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 2725 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/368/07368964.pdf [firstpage_image] =>[orig_patent_app_number] => 11320847 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/320847
Delay locked loop in semiconductor memory device and method for generating divided clock therein Dec 29, 2005 Issued
Array ( [id] => 540559 [patent_doc_number] => 07173463 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-06 [patent_title] => 'Generating multi-phase clock signals using hierarchical delays' [patent_app_type] => utility [patent_app_number] => 11/313291 [patent_app_country] => US [patent_app_date] => 2005-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3714 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 24 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/173/07173463.pdf [firstpage_image] =>[orig_patent_app_number] => 11313291 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/313291
Generating multi-phase clock signals using hierarchical delays Dec 19, 2005 Issued
Array ( [id] => 5251035 [patent_doc_number] => 20070132491 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-14 [patent_title] => 'PHASE-LOCKED LOOP WITH COMPENSATED LOOP BANDWIDTH' [patent_app_type] => utility [patent_app_number] => 11/164956 [patent_app_country] => US [patent_app_date] => 2005-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 4869 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0132/20070132491.pdf [firstpage_image] =>[orig_patent_app_number] => 11164956 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/164956
PHASE-LOCKED LOOP WITH COMPENSATED LOOP BANDWIDTH Dec 11, 2005 Abandoned
Array ( [id] => 398253 [patent_doc_number] => 07295045 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-11-13 [patent_title] => 'Circuit for cutting-off output signal' [patent_app_type] => utility [patent_app_number] => 11/296464 [patent_app_country] => US [patent_app_date] => 2005-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3094 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/295/07295045.pdf [firstpage_image] =>[orig_patent_app_number] => 11296464 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/296464
Circuit for cutting-off output signal Dec 7, 2005 Issued
Array ( [id] => 492342 [patent_doc_number] => 07215174 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-05-08 [patent_title] => 'Method and apparatus for implementing a radiation hardened N-channel transistor with the use of non-radiation hardened transistors' [patent_app_type] => utility [patent_app_number] => 11/295985 [patent_app_country] => US [patent_app_date] => 2005-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1705 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/215/07215174.pdf [firstpage_image] =>[orig_patent_app_number] => 11295985 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/295985
Method and apparatus for implementing a radiation hardened N-channel transistor with the use of non-radiation hardened transistors Dec 6, 2005 Issued
Array ( [id] => 537959 [patent_doc_number] => 07180347 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-20 [patent_title] => 'Systems and methods for minimizing harmonic interference' [patent_app_type] => utility [patent_app_number] => 11/297183 [patent_app_country] => US [patent_app_date] => 2005-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 2376 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/180/07180347.pdf [firstpage_image] =>[orig_patent_app_number] => 11297183 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/297183
Systems and methods for minimizing harmonic interference Dec 5, 2005 Issued
Array ( [id] => 911786 [patent_doc_number] => 07330056 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-02-12 [patent_title] => 'Low power CMOS LVDS driver' [patent_app_type] => utility [patent_app_number] => 11/296187 [patent_app_country] => US [patent_app_date] => 2005-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1633 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/330/07330056.pdf [firstpage_image] =>[orig_patent_app_number] => 11296187 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/296187
Low power CMOS LVDS driver Dec 5, 2005 Issued
Array ( [id] => 5234333 [patent_doc_number] => 20070126488 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-07 [patent_title] => 'Triggering events at fractions of a clock cycle' [patent_app_type] => utility [patent_app_number] => 11/292477 [patent_app_country] => US [patent_app_date] => 2005-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5416 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0126/20070126488.pdf [firstpage_image] =>[orig_patent_app_number] => 11292477 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/292477
Triggering events at fractions of a clock cycle Dec 1, 2005 Issued
Array ( [id] => 5077360 [patent_doc_number] => 20070120584 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-31 [patent_title] => 'PHASE- OR FREQUENCY-LOCKED LOOP CIRCUIT HAVING A GLITCH DETECTOR FOR DETECTING TRIGGERING-EDGE-TYPE GLITCHES IN A NOISY SIGNAL' [patent_app_type] => utility [patent_app_number] => 11/164637 [patent_app_country] => US [patent_app_date] => 2005-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4939 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0120/20070120584.pdf [firstpage_image] =>[orig_patent_app_number] => 11164637 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/164637
Phase- or frequency-locked loop circuit having a glitch detector for detecting triggering-edge-type glitches in a noisy signal Nov 29, 2005 Issued
Array ( [id] => 7602995 [patent_doc_number] => 07236039 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-06-26 [patent_title] => 'Spread spectrum clock generating apparatus' [patent_app_type] => utility [patent_app_number] => 11/289599 [patent_app_country] => US [patent_app_date] => 2005-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 9719 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/236/07236039.pdf [firstpage_image] =>[orig_patent_app_number] => 11289599 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/289599
Spread spectrum clock generating apparatus Nov 29, 2005 Issued
Array ( [id] => 422287 [patent_doc_number] => 07274221 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-09-25 [patent_title] => 'Comparator circuit' [patent_app_type] => utility [patent_app_number] => 11/288717 [patent_app_country] => US [patent_app_date] => 2005-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4318 [patent_no_of_claims] => 64 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/274/07274221.pdf [firstpage_image] =>[orig_patent_app_number] => 11288717 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/288717
Comparator circuit Nov 28, 2005 Issued
Array ( [id] => 5612114 [patent_doc_number] => 20060114040 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-01 [patent_title] => 'Phase synchronization circuit and semiconductor integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/288176 [patent_app_country] => US [patent_app_date] => 2005-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 11637 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0114/20060114040.pdf [firstpage_image] =>[orig_patent_app_number] => 11288176 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/288176
Phase synchronization circuit and semiconductor integrated circuit Nov 28, 2005 Issued
Array ( [id] => 5251052 [patent_doc_number] => 20070132508 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-14 [patent_title] => 'Multi-phase power supply controller and method therefor' [patent_app_type] => utility [patent_app_number] => 11/286979 [patent_app_country] => US [patent_app_date] => 2005-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 12203 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0132/20070132508.pdf [firstpage_image] =>[orig_patent_app_number] => 11286979 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/286979
Multi-phase power supply controller and method therefor Nov 27, 2005 Issued
Array ( [id] => 5612125 [patent_doc_number] => 20060114051 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-01 [patent_title] => 'High-frequency switch circuit arrangement' [patent_app_type] => utility [patent_app_number] => 11/285152 [patent_app_country] => US [patent_app_date] => 2005-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7778 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0114/20060114051.pdf [firstpage_image] =>[orig_patent_app_number] => 11285152 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/285152
High-frequency switch circuit arrangement Nov 22, 2005 Issued
Array ( [id] => 5093433 [patent_doc_number] => 20070115042 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-24 [patent_title] => 'Accurate temperature measurement method for low beta transistors' [patent_app_type] => utility [patent_app_number] => 11/286706 [patent_app_country] => US [patent_app_date] => 2005-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5833 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0115/20070115042.pdf [firstpage_image] =>[orig_patent_app_number] => 11286706 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/286706
Accurate temperature measurement method for low beta transistors Nov 22, 2005 Issued
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