
An T. Luu
Examiner (ID: 5797, Phone: (571)272-1746 , Office: P/2842 )
| Most Active Art Unit | 2816 |
| Art Unit(s) | 2502, 2816, 2842 |
| Total Applications | 2105 |
| Issued Applications | 1967 |
| Pending Applications | 23 |
| Abandoned Applications | 118 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 387177
[patent_doc_number] => 07304547
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-12-04
[patent_title] => 'Method and apparatus to improve frequency stability of an integrated circuit oscillator'
[patent_app_type] => utility
[patent_app_number] => 11/360184
[patent_app_country] => US
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[pdf_file] => patents/07/304/07304547.pdf
[firstpage_image] =>[orig_patent_app_number] => 11360184
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Array
(
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[patent_doc_number] => 20060139108
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[patent_kind] => A1
[patent_issue_date] => 2006-06-29
[patent_title] => 'Controlling a voltage controlled oscillator in a bang-bang phase locked loop'
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[patent_app_date] => 2006-02-17
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Array
(
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[patent_doc_number] => 07619462
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[patent_kind] => B2
[patent_issue_date] => 2009-11-17
[patent_title] => 'Unpowered switch and bleeder circuit'
[patent_app_type] => utility
[patent_app_number] => 11/351342
[patent_app_country] => US
[patent_app_date] => 2006-02-09
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[patent_drawing_sheets_cnt] => 9
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[firstpage_image] =>[orig_patent_app_number] => 11351342
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/351342 | Unpowered switch and bleeder circuit | Feb 8, 2006 | Issued |
Array
(
[id] => 458337
[patent_doc_number] => 07245166
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-07-17
[patent_title] => 'Starter circuit'
[patent_app_type] => utility
[patent_app_number] => 11/332177
[patent_app_country] => US
[patent_app_date] => 2006-01-17
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[firstpage_image] =>[orig_patent_app_number] => 11332177
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/332177 | Starter circuit | Jan 16, 2006 | Issued |
Array
(
[id] => 398254
[patent_doc_number] => 07295046
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[patent_issue_date] => 2007-11-13
[patent_title] => 'Power down detection circuit'
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[firstpage_image] =>[orig_patent_app_number] => 11327990
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/327990 | Power down detection circuit | Jan 8, 2006 | Issued |
Array
(
[id] => 865914
[patent_doc_number] => 07368964
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-05-06
[patent_title] => 'Delay locked loop in semiconductor memory device and method for generating divided clock therein'
[patent_app_type] => utility
[patent_app_number] => 11/320847
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[patent_app_date] => 2005-12-30
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[pdf_file] => patents/07/368/07368964.pdf
[firstpage_image] =>[orig_patent_app_number] => 11320847
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/320847 | Delay locked loop in semiconductor memory device and method for generating divided clock therein | Dec 29, 2005 | Issued |
Array
(
[id] => 540559
[patent_doc_number] => 07173463
[patent_country] => US
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[patent_issue_date] => 2007-02-06
[patent_title] => 'Generating multi-phase clock signals using hierarchical delays'
[patent_app_type] => utility
[patent_app_number] => 11/313291
[patent_app_country] => US
[patent_app_date] => 2005-12-20
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[pdf_file] => patents/07/173/07173463.pdf
[firstpage_image] =>[orig_patent_app_number] => 11313291
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/313291 | Generating multi-phase clock signals using hierarchical delays | Dec 19, 2005 | Issued |
Array
(
[id] => 5251035
[patent_doc_number] => 20070132491
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-06-14
[patent_title] => 'PHASE-LOCKED LOOP WITH COMPENSATED LOOP BANDWIDTH'
[patent_app_type] => utility
[patent_app_number] => 11/164956
[patent_app_country] => US
[patent_app_date] => 2005-12-12
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[pdf_file] => publications/A1/0132/20070132491.pdf
[firstpage_image] =>[orig_patent_app_number] => 11164956
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/164956 | PHASE-LOCKED LOOP WITH COMPENSATED LOOP BANDWIDTH | Dec 11, 2005 | Abandoned |
Array
(
[id] => 398253
[patent_doc_number] => 07295045
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-11-13
[patent_title] => 'Circuit for cutting-off output signal'
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[firstpage_image] =>[orig_patent_app_number] => 11296464
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/296464 | Circuit for cutting-off output signal | Dec 7, 2005 | Issued |
Array
(
[id] => 492342
[patent_doc_number] => 07215174
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[patent_issue_date] => 2007-05-08
[patent_title] => 'Method and apparatus for implementing a radiation hardened N-channel transistor with the use of non-radiation hardened transistors'
[patent_app_type] => utility
[patent_app_number] => 11/295985
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[pdf_file] => patents/07/215/07215174.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/295985 | Method and apparatus for implementing a radiation hardened N-channel transistor with the use of non-radiation hardened transistors | Dec 6, 2005 | Issued |
Array
(
[id] => 537959
[patent_doc_number] => 07180347
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[patent_issue_date] => 2007-02-20
[patent_title] => 'Systems and methods for minimizing harmonic interference'
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[firstpage_image] =>[orig_patent_app_number] => 11297183
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/297183 | Systems and methods for minimizing harmonic interference | Dec 5, 2005 | Issued |
Array
(
[id] => 911786
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[patent_title] => 'Low power CMOS LVDS driver'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/296187 | Low power CMOS LVDS driver | Dec 5, 2005 | Issued |
Array
(
[id] => 5234333
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[patent_title] => 'Triggering events at fractions of a clock cycle'
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Array
(
[id] => 5077360
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[patent_title] => 'PHASE- OR FREQUENCY-LOCKED LOOP CIRCUIT HAVING A GLITCH DETECTOR FOR DETECTING TRIGGERING-EDGE-TYPE GLITCHES IN A NOISY SIGNAL'
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[firstpage_image] =>[orig_patent_app_number] => 11164637
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/164637 | Phase- or frequency-locked loop circuit having a glitch detector for detecting triggering-edge-type glitches in a noisy signal | Nov 29, 2005 | Issued |
Array
(
[id] => 7602995
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/289599 | Spread spectrum clock generating apparatus | Nov 29, 2005 | Issued |
Array
(
[id] => 422287
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Array
(
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Array
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Array
(
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/286706 | Accurate temperature measurement method for low beta transistors | Nov 22, 2005 | Issued |