
An T. Luu
Examiner (ID: 5797, Phone: (571)272-1746 , Office: P/2842 )
| Most Active Art Unit | 2816 |
| Art Unit(s) | 2502, 2816, 2842 |
| Total Applications | 2105 |
| Issued Applications | 1967 |
| Pending Applications | 23 |
| Abandoned Applications | 118 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 480821
[patent_doc_number] => 07224199
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[patent_kind] => B1
[patent_issue_date] => 2007-05-29
[patent_title] => 'Circuit and method for digital delay and circuits incorporating the same'
[patent_app_type] => utility
[patent_app_number] => 11/267415
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[pdf_file] => patents/07/224/07224199.pdf
[firstpage_image] =>[orig_patent_app_number] => 11267415
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Array
(
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[patent_doc_number] => 07417488
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[patent_kind] => B2
[patent_issue_date] => 2008-08-26
[patent_title] => 'Regulation circuit for inductive charge pump'
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[firstpage_image] =>[orig_patent_app_number] => 11266218
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/266218 | Regulation circuit for inductive charge pump | Nov 3, 2005 | Issued |
Array
(
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[patent_doc_number] => 20060097762
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[patent_kind] => A1
[patent_issue_date] => 2006-05-11
[patent_title] => 'Delay locked loop and semiconductor memory device having the same'
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[patent_app_date] => 2005-11-03
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Array
(
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[patent_issue_date] => 2007-05-03
[patent_title] => 'Method for improving the timing resolution of DLL controlled delay lines'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/265962 | Method for improving the timing resolution of DLL controlled delay lines | Nov 2, 2005 | Abandoned |
Array
(
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[patent_title] => 'Variable time constant circuit and filter circuit using the same'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/258934 | Variable time constant circuit and filter circuit using the same | Oct 26, 2005 | Issued |
Array
(
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[patent_issue_date] => 2006-02-23
[patent_title] => 'Clock signal distribution utilizing differential sinusoidal signal pair'
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Array
(
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[patent_title] => 'Digital delay-locked loop circuits with hierarchical delay adjustment'
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[firstpage_image] =>[orig_patent_app_number] => 11256215
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/256215 | Digital delay-locked loop circuits with hierarchical delay adjustment | Oct 20, 2005 | Issued |
Array
(
[id] => 5746128
[patent_doc_number] => 20060109058
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[patent_kind] => A1
[patent_issue_date] => 2006-05-25
[patent_title] => 'Clock oscillator'
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[patent_app_number] => 11/255094
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/255094 | Clock oscillator | Oct 18, 2005 | Issued |
Array
(
[id] => 5134123
[patent_doc_number] => 20070075752
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-04-05
[patent_title] => 'Digital programmable frequency divider'
[patent_app_type] => utility
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[firstpage_image] =>[orig_patent_app_number] => 11243022
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/243022 | Digital programmable frequency divider | Oct 3, 2005 | Abandoned |
Array
(
[id] => 5134829
[patent_doc_number] => 20070076458
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[patent_issue_date] => 2007-04-05
[patent_title] => 'Timing control circuit for lossless switching converter'
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[patent_app_number] => 11/239881
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[firstpage_image] =>[orig_patent_app_number] => 11239881
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/239881 | Timing control circuit for lossless switching converter | Sep 29, 2005 | Issued |
Array
(
[id] => 5478095
[patent_doc_number] => 20090201052
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[patent_kind] => A1
[patent_issue_date] => 2009-08-13
[patent_title] => 'LOW VOLTAGE, HIGH-SPEED OUTPUT-STAGE FOR LASER OR MODULATOR DRIVING'
[patent_app_type] => utility
[patent_app_number] => 11/577182
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[firstpage_image] =>[orig_patent_app_number] => 11577182
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/577182 | Low voltage, high-speed output-stage for laser or modulator driving | Sep 29, 2005 | Issued |
Array
(
[id] => 4680291
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[patent_title] => 'Sample and Hold Circuits'
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Array
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[patent_title] => 'Fast Pulse Generator'
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Array
(
[id] => 896597
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/221187 | Method and apparatus for a symmetrical odd-number clock divider | Sep 6, 2005 | Issued |
Array
(
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Array
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Array
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Array
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/204284 | Digital dead-time controller for pulse width modulators | Aug 13, 2005 | Issued |