Search

An T. Luu

Examiner (ID: 5797, Phone: (571)272-1746 , Office: P/2842 )

Most Active Art Unit
2816
Art Unit(s)
2502, 2816, 2842
Total Applications
2105
Issued Applications
1967
Pending Applications
23
Abandoned Applications
118

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 480821 [patent_doc_number] => 07224199 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-05-29 [patent_title] => 'Circuit and method for digital delay and circuits incorporating the same' [patent_app_type] => utility [patent_app_number] => 11/267415 [patent_app_country] => US [patent_app_date] => 2005-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 21 [patent_no_of_words] => 10151 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/224/07224199.pdf [firstpage_image] =>[orig_patent_app_number] => 11267415 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/267415
Circuit and method for digital delay and circuits incorporating the same Nov 3, 2005 Issued
Array ( [id] => 810847 [patent_doc_number] => 07417488 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-08-26 [patent_title] => 'Regulation circuit for inductive charge pump' [patent_app_type] => utility [patent_app_number] => 11/266218 [patent_app_country] => US [patent_app_date] => 2005-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 4940 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/417/07417488.pdf [firstpage_image] =>[orig_patent_app_number] => 11266218 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/266218
Regulation circuit for inductive charge pump Nov 3, 2005 Issued
Array ( [id] => 5863632 [patent_doc_number] => 20060097762 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-11 [patent_title] => 'Delay locked loop and semiconductor memory device having the same' [patent_app_type] => utility [patent_app_number] => 11/265945 [patent_app_country] => US [patent_app_date] => 2005-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8153 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0097/20060097762.pdf [firstpage_image] =>[orig_patent_app_number] => 11265945 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/265945
Delay locked loop and semiconductor memory device having the same Nov 2, 2005 Issued
Array ( [id] => 5032248 [patent_doc_number] => 20070096787 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-03 [patent_title] => 'Method for improving the timing resolution of DLL controlled delay lines' [patent_app_type] => utility [patent_app_number] => 11/265962 [patent_app_country] => US [patent_app_date] => 2005-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3809 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0096/20070096787.pdf [firstpage_image] =>[orig_patent_app_number] => 11265962 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/265962
Method for improving the timing resolution of DLL controlled delay lines Nov 2, 2005 Abandoned
Array ( [id] => 643199 [patent_doc_number] => 07123082 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-17 [patent_title] => 'Variable time constant circuit and filter circuit using the same' [patent_app_type] => utility [patent_app_number] => 11/258934 [patent_app_country] => US [patent_app_date] => 2005-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 5444 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 404 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/123/07123082.pdf [firstpage_image] =>[orig_patent_app_number] => 11258934 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/258934
Variable time constant circuit and filter circuit using the same Oct 26, 2005 Issued
Array ( [id] => 5589151 [patent_doc_number] => 20060038602 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-23 [patent_title] => 'Clock signal distribution utilizing differential sinusoidal signal pair' [patent_app_type] => utility [patent_app_number] => 11/255707 [patent_app_country] => US [patent_app_date] => 2005-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2363 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0038/20060038602.pdf [firstpage_image] =>[orig_patent_app_number] => 11255707 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/255707
Clock signal distribution utilizing differential sinusoidal signal pair Oct 20, 2005 Issued
Array ( [id] => 634993 [patent_doc_number] => 07129761 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-31 [patent_title] => 'Digital delay-locked loop circuits with hierarchical delay adjustment' [patent_app_type] => utility [patent_app_number] => 11/256215 [patent_app_country] => US [patent_app_date] => 2005-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6045 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/129/07129761.pdf [firstpage_image] =>[orig_patent_app_number] => 11256215 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/256215
Digital delay-locked loop circuits with hierarchical delay adjustment Oct 20, 2005 Issued
Array ( [id] => 5746128 [patent_doc_number] => 20060109058 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-25 [patent_title] => 'Clock oscillator' [patent_app_type] => utility [patent_app_number] => 11/255094 [patent_app_country] => US [patent_app_date] => 2005-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2347 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20060109058.pdf [firstpage_image] =>[orig_patent_app_number] => 11255094 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/255094
Clock oscillator Oct 18, 2005 Issued
Array ( [id] => 5134123 [patent_doc_number] => 20070075752 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-05 [patent_title] => 'Digital programmable frequency divider' [patent_app_type] => utility [patent_app_number] => 11/243022 [patent_app_country] => US [patent_app_date] => 2005-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2576 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0075/20070075752.pdf [firstpage_image] =>[orig_patent_app_number] => 11243022 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/243022
Digital programmable frequency divider Oct 3, 2005 Abandoned
Array ( [id] => 5134829 [patent_doc_number] => 20070076458 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-05 [patent_title] => 'Timing control circuit for lossless switching converter' [patent_app_type] => utility [patent_app_number] => 11/239881 [patent_app_country] => US [patent_app_date] => 2005-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3712 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0076/20070076458.pdf [firstpage_image] =>[orig_patent_app_number] => 11239881 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/239881
Timing control circuit for lossless switching converter Sep 29, 2005 Issued
Array ( [id] => 5478095 [patent_doc_number] => 20090201052 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-13 [patent_title] => 'LOW VOLTAGE, HIGH-SPEED OUTPUT-STAGE FOR LASER OR MODULATOR DRIVING' [patent_app_type] => utility [patent_app_number] => 11/577182 [patent_app_country] => US [patent_app_date] => 2005-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5547 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0201/20090201052.pdf [firstpage_image] =>[orig_patent_app_number] => 11577182 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/577182
Low voltage, high-speed output-stage for laser or modulator driving Sep 29, 2005 Issued
Array ( [id] => 4680291 [patent_doc_number] => 20080246517 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-09 [patent_title] => 'Sample and Hold Circuits' [patent_app_type] => utility [patent_app_number] => 11/664044 [patent_app_country] => US [patent_app_date] => 2005-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2935 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0246/20080246517.pdf [firstpage_image] =>[orig_patent_app_number] => 11664044 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/664044
Sample and Hold Circuits Sep 27, 2005 Abandoned
Array ( [id] => 4673921 [patent_doc_number] => 20080211549 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-04 [patent_title] => 'Fast Pulse Generator' [patent_app_type] => utility [patent_app_number] => 11/575696 [patent_app_country] => US [patent_app_date] => 2005-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1063 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0211/20080211549.pdf [firstpage_image] =>[orig_patent_app_number] => 11575696 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/575696
Fast pulse generator Sep 20, 2005 Issued
Array ( [id] => 896597 [patent_doc_number] => 07342425 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-03-11 [patent_title] => 'Method and apparatus for a symmetrical odd-number clock divider' [patent_app_type] => utility [patent_app_number] => 11/221187 [patent_app_country] => US [patent_app_date] => 2005-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3041 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/342/07342425.pdf [firstpage_image] =>[orig_patent_app_number] => 11221187 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/221187
Method and apparatus for a symmetrical odd-number clock divider Sep 6, 2005 Issued
Array ( [id] => 4981692 [patent_doc_number] => 20070086250 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-19 [patent_title] => 'Measure control delay and method having latching circuit integral with delay circuit' [patent_app_type] => utility [patent_app_number] => 11/219302 [patent_app_country] => US [patent_app_date] => 2005-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7021 [patent_no_of_claims] => 57 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0086/20070086250.pdf [firstpage_image] =>[orig_patent_app_number] => 11219302 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/219302
Measure control delay and method having latching circuit integral with delay circuit Aug 31, 2005 Issued
Array ( [id] => 5146289 [patent_doc_number] => 20070046343 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-01 [patent_title] => 'PLL with controlled VCO bias' [patent_app_type] => utility [patent_app_number] => 11/218207 [patent_app_country] => US [patent_app_date] => 2005-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3403 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20070046343.pdf [firstpage_image] =>[orig_patent_app_number] => 11218207 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/218207
PLL with controlled VCO bias Aug 30, 2005 Issued
Array ( [id] => 6975929 [patent_doc_number] => 20050285644 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-29 [patent_title] => 'Apparatus and method for suppressing jitter within a clock signal generator' [patent_app_type] => utility [patent_app_number] => 11/216416 [patent_app_country] => US [patent_app_date] => 2005-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9584 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0285/20050285644.pdf [firstpage_image] =>[orig_patent_app_number] => 11216416 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/216416
Apparatus and method for suppressing jitter within a clock signal generator Aug 29, 2005 Issued
Array ( [id] => 5146287 [patent_doc_number] => 20070046341 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-01 [patent_title] => 'Method and apparatus for generating a power on reset with a low temperature coefficient' [patent_app_type] => utility [patent_app_number] => 11/215802 [patent_app_country] => US [patent_app_date] => 2005-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4917 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20070046341.pdf [firstpage_image] =>[orig_patent_app_number] => 11215802 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/215802
Method and apparatus for generating a power on reset with a low temperature coefficient Aug 28, 2005 Abandoned
Array ( [id] => 5146290 [patent_doc_number] => 20070046344 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-01 [patent_title] => 'Delay locked loop using a FIFO circuit to synchronize between blender and coarse delay control signals' [patent_app_type] => utility [patent_app_number] => 11/211825 [patent_app_country] => US [patent_app_date] => 2005-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7291 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20070046344.pdf [firstpage_image] =>[orig_patent_app_number] => 11211825 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/211825
Delay locked loop using a FIFO circuit to synchronize between blender and coarse delay control signals Aug 24, 2005 Issued
Array ( [id] => 282371 [patent_doc_number] => 07554372 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-06-30 [patent_title] => 'Digital dead-time controller for pulse width modulators' [patent_app_type] => utility [patent_app_number] => 11/204284 [patent_app_country] => US [patent_app_date] => 2005-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 20 [patent_no_of_words] => 6813 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/554/07554372.pdf [firstpage_image] =>[orig_patent_app_number] => 11204284 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/204284
Digital dead-time controller for pulse width modulators Aug 13, 2005 Issued
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