An T. Luu

Array ( [id] => 334826 [patent_doc_number] => 07508239 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-24 [patent_title] => 'Pattern sequence and state transition triggers' [patent_app_type] => utility [patent_app_number] => 11/202595 [patent_app_country] => US [patent_app_date] => 2005-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2281 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/508/07508239.pdf [firstpage_image] =>[orig_patent_app_number] => 11202595 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 444137 [patent_doc_number] => 07256643 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-08-14 [patent_title] => 'Device and method for generating a low-voltage reference' [patent_app_type] => utility [patent_app_number] => 11/196978 [patent_app_country] => US [patent_app_date] => 2005-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 5120 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/256/07256643.pdf [firstpage_image] =>[orig_patent_app_number] => 11196978 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 398261 [patent_doc_number] => 07295052 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-11-13 [patent_title] => 'Regenerative power-on control circuit' [patent_app_type] => utility [patent_app_number] => 11/196715 [patent_app_country] => US [patent_app_date] => 2005-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3909 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/295/07295052.pdf [firstpage_image] =>[orig_patent_app_number] => 11196715 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 440545 [patent_doc_number] => 07259604 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-08-21 [patent_title] => 'Initialization scheme for a reduced-frequency, fifty percent duty cycle corrector' [patent_app_type] => utility [patent_app_number] => 11/196581 [patent_app_country] => US [patent_app_date] => 2005-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 11014 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/259/07259604.pdf [firstpage_image] =>[orig_patent_app_number] => 11196581 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6975928 [patent_doc_number] => 20050285643 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-29 [patent_title] => 'Digital frequency-multiplying DLLs' [patent_app_type] => utility [patent_app_number] => 11/195154 [patent_app_country] => US [patent_app_date] => 2005-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3954 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0285/20050285643.pdf [firstpage_image] =>[orig_patent_app_number] => 11195154 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5240224 [patent_doc_number] => 20070018715 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-25 [patent_title] => 'Clocked standby mode with maximum clock frequency' [patent_app_type] => utility [patent_app_number] => 11/187546 [patent_app_country] => US [patent_app_date] => 2005-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7333 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0018/20070018715.pdf [firstpage_image] =>[orig_patent_app_number] => 11187546 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7216828 [patent_doc_number] => 20050253632 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-17 [patent_title] => 'Low-power direct digital synthesizer with analog interpolation' [patent_app_type] => utility [patent_app_number] => 11/186451 [patent_app_country] => US [patent_app_date] => 2005-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8127 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0253/20050253632.pdf [firstpage_image] =>[orig_patent_app_number] => 11186451 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5139509 [patent_doc_number] => 20070001725 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-04 [patent_title] => 'APPARATUS AND A METHOD TO PROVIDE TIME-BASED EDGE-RATE COMPENSATION' [patent_app_type] => utility [patent_app_number] => 11/171574 [patent_app_country] => US [patent_app_date] => 2005-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4049 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20070001725.pdf [firstpage_image] =>[orig_patent_app_number] => 11171574 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 470097 [patent_doc_number] => 07233184 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-06-19 [patent_title] => 'Method and apparatus for a configurable latch' [patent_app_type] => utility [patent_app_number] => 11/158523 [patent_app_country] => US [patent_app_date] => 2005-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5153 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/233/07233184.pdf [firstpage_image] =>[orig_patent_app_number] => 11158523 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 394493 [patent_doc_number] => 07298194 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-11-20 [patent_title] => 'Interpolation' [patent_app_type] => utility [patent_app_number] => 11/151335 [patent_app_country] => US [patent_app_date] => 2005-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1271 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/298/07298194.pdf [firstpage_image] =>[orig_patent_app_number] => 11151335 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4907599 [patent_doc_number] => 20080018365 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-24 [patent_title] => 'Coil Load Drive Output Circuit' [patent_app_type] => utility [patent_app_number] => 11/569946 [patent_app_country] => US [patent_app_date] => 2005-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3410 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0018/20080018365.pdf [firstpage_image] =>[orig_patent_app_number] => 11569946 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7589179 [patent_doc_number] => 07663414 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-02-16 [patent_title] => 'Prescaling stage for high frequency applications' [patent_app_type] => utility [patent_app_number] => 11/141252 [patent_app_country] => US [patent_app_date] => 2005-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4455 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/663/07663414.pdf [firstpage_image] =>[orig_patent_app_number] => 11141252 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7602997 [patent_doc_number] => 07236037 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-06-26 [patent_title] => 'Alternating clock signal generation for delay loops' [patent_app_type] => utility [patent_app_number] => 11/138777 [patent_app_country] => US [patent_app_date] => 2005-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5066 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/236/07236037.pdf [firstpage_image] =>[orig_patent_app_number] => 11138777 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 153286 [patent_doc_number] => 07679416 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-16 [patent_title] => 'High speed clock distribution transmission line network' [patent_app_type] => utility [patent_app_number] => 11/596968 [patent_app_country] => US [patent_app_date] => 2005-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4835 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/679/07679416.pdf [firstpage_image] =>[orig_patent_app_number] => 11596968 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7231653 [patent_doc_number] => 20050270083 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-08 [patent_title] => 'Radio frequency switching circuit and semiconductor device using the same' [patent_app_type] => utility [patent_app_number] => 11/134351 [patent_app_country] => US [patent_app_date] => 2005-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 15559 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 18 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0270/20050270083.pdf [firstpage_image] =>[orig_patent_app_number] => 11134351 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 429156 [patent_doc_number] => 07268594 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-09-11 [patent_title] => 'Direct digital synthesis with low jitter' [patent_app_type] => utility [patent_app_number] => 11/128774 [patent_app_country] => US [patent_app_date] => 2005-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3886 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/268/07268594.pdf [firstpage_image] =>[orig_patent_app_number] => 11128774 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7044401 [patent_doc_number] => 20050248996 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-10 [patent_title] => 'Integrated circuit for stabilizing a voltage' [patent_app_type] => utility [patent_app_number] => 11/123226 [patent_app_country] => US [patent_app_date] => 2005-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6164 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0248/20050248996.pdf [firstpage_image] =>[orig_patent_app_number] => 11123226 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 114328 [patent_doc_number] => 07714631 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-11 [patent_title] => 'Method and apparatus for synchronizing a clock generator in the presence of jittery clock sources' [patent_app_type] => utility [patent_app_number] => 11/596241 [patent_app_country] => US [patent_app_date] => 2005-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4433 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/714/07714631.pdf [firstpage_image] =>[orig_patent_app_number] => 11596241 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 566320 [patent_doc_number] => 07157953 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-01-02 [patent_title] => 'Circuit for and method of employing a clock signal' [patent_app_type] => utility [patent_app_number] => 11/104347 [patent_app_country] => US [patent_app_date] => 2005-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4588 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/157/07157953.pdf [firstpage_image] =>[orig_patent_app_number] => 11104347 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5854952 [patent_doc_number] => 20060226885 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-12 [patent_title] => 'Apparatus and method for generating pulses' [patent_app_type] => utility [patent_app_number] => 11/104030 [patent_app_country] => US [patent_app_date] => 2005-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4890 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0226/20060226885.pdf [firstpage_image] =>[orig_patent_app_number] => 11104030 [rel_patent_id] =>[rel_patent_doc_number] =>)