Search

An T. Luu

Examiner (ID: 5797, Phone: (571)272-1746 , Office: P/2842 )

Most Active Art Unit
2816
Art Unit(s)
2502, 2816, 2842
Total Applications
2105
Issued Applications
1967
Pending Applications
23
Abandoned Applications
118

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7505445 [patent_doc_number] => 08035421 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-10-11 [patent_title] => 'Versatile charge sampling circuits' [patent_app_type] => utility [patent_app_number] => 11/099460 [patent_app_country] => US [patent_app_date] => 2005-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 27 [patent_no_of_words] => 6199 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/035/08035421.pdf [firstpage_image] =>[orig_patent_app_number] => 11099460 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/099460
Versatile charge sampling circuits Apr 5, 2005 Issued
Array ( [id] => 5751559 [patent_doc_number] => 20060220708 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-05 [patent_title] => 'Digital clock frequency doubler' [patent_app_type] => utility [patent_app_number] => 11/098107 [patent_app_country] => US [patent_app_date] => 2005-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2679 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0220/20060220708.pdf [firstpage_image] =>[orig_patent_app_number] => 11098107 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/098107
Digital clock frequency doubler Apr 3, 2005 Issued
Array ( [id] => 7133570 [patent_doc_number] => 20050179480 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-18 [patent_title] => 'Level shifter and flat panel display' [patent_app_type] => utility [patent_app_number] => 11/097489 [patent_app_country] => US [patent_app_date] => 2005-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4834 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0179/20050179480.pdf [firstpage_image] =>[orig_patent_app_number] => 11097489 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/097489
Level shifter and flat panel display Mar 31, 2005 Issued
Array ( [id] => 5751570 [patent_doc_number] => 20060220719 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-05 [patent_title] => 'Methods and apparatus for improved phase switching and linearity in an analog phase interpolator' [patent_app_type] => utility [patent_app_number] => 11/095771 [patent_app_country] => US [patent_app_date] => 2005-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2706 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0220/20060220719.pdf [firstpage_image] =>[orig_patent_app_number] => 11095771 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/095771
Methods and apparatus for improved phase switching and linearity in an analog phase interpolator Mar 30, 2005 Issued
Array ( [id] => 477182 [patent_doc_number] => 07227397 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-06-05 [patent_title] => 'System, method and circuits for generating a signal' [patent_app_type] => utility [patent_app_number] => 11/096770 [patent_app_country] => US [patent_app_date] => 2005-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3072 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/227/07227397.pdf [firstpage_image] =>[orig_patent_app_number] => 11096770 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/096770
System, method and circuits for generating a signal Mar 30, 2005 Issued
Array ( [id] => 5751571 [patent_doc_number] => 20060220720 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-05 [patent_title] => 'Methods and apparatus for maintaining desired slope of clock edges in a phase interpolator using an adjustable bias' [patent_app_type] => utility [patent_app_number] => 11/095772 [patent_app_country] => US [patent_app_date] => 2005-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1861 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0220/20060220720.pdf [firstpage_image] =>[orig_patent_app_number] => 11095772 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/095772
Methods and apparatus for maintaining desired slope of clock edges in a phase interpolator using an adjustable bias Mar 30, 2005 Issued
Array ( [id] => 5698041 [patent_doc_number] => 20060214725 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-28 [patent_title] => 'Digital time constant tracking technique and apparatus' [patent_app_type] => utility [patent_app_number] => 11/089963 [patent_app_country] => US [patent_app_date] => 2005-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3712 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0214/20060214725.pdf [firstpage_image] =>[orig_patent_app_number] => 11089963 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/089963
Digital time constant tracking technique and apparatus Mar 24, 2005 Issued
Array ( [id] => 537975 [patent_doc_number] => 07180348 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-20 [patent_title] => 'Circuit and method for storing data in operational and sleep modes' [patent_app_type] => utility [patent_app_number] => 11/088268 [patent_app_country] => US [patent_app_date] => 2005-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5400 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/180/07180348.pdf [firstpage_image] =>[orig_patent_app_number] => 11088268 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/088268
Circuit and method for storing data in operational and sleep modes Mar 23, 2005 Issued
Array ( [id] => 5698016 [patent_doc_number] => 20060214700 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-28 [patent_title] => 'Stable systems for comparing and converting signals' [patent_app_type] => utility [patent_app_number] => 11/088364 [patent_app_country] => US [patent_app_date] => 2005-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4724 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0214/20060214700.pdf [firstpage_image] =>[orig_patent_app_number] => 11088364 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/088364
Stable systems for comparing and converting signals Mar 22, 2005 Issued
Array ( [id] => 6956199 [patent_doc_number] => 20050212569 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-29 [patent_title] => 'Input circuit and output circuit' [patent_app_type] => utility [patent_app_number] => 11/087120 [patent_app_country] => US [patent_app_date] => 2005-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3664 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0212/20050212569.pdf [firstpage_image] =>[orig_patent_app_number] => 11087120 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/087120
Input circuit and output circuit Mar 22, 2005 Issued
Array ( [id] => 959145 [patent_doc_number] => 06954092 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-10-11 [patent_title] => 'Charge pump circuit and PLL circuit using same' [patent_app_type] => utility [patent_app_number] => 11/085559 [patent_app_country] => US [patent_app_date] => 2005-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 25 [patent_no_of_words] => 10903 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 366 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/954/06954092.pdf [firstpage_image] =>[orig_patent_app_number] => 11085559 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/085559
Charge pump circuit and PLL circuit using same Mar 21, 2005 Issued
Array ( [id] => 7185166 [patent_doc_number] => 20050162201 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-28 [patent_title] => 'Charge pump circuit and PLL circuit using same' [patent_app_type] => utility [patent_app_number] => 11/085537 [patent_app_country] => US [patent_app_date] => 2005-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10916 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0162/20050162201.pdf [firstpage_image] =>[orig_patent_app_number] => 11085537 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/085537
Charge pump circuit and PLL circuit using same Mar 21, 2005 Issued
Array ( [id] => 926048 [patent_doc_number] => 07317346 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-01-08 [patent_title] => 'Selecting a bias for a level shifting device' [patent_app_type] => utility [patent_app_number] => 11/076970 [patent_app_country] => US [patent_app_date] => 2005-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2231 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/317/07317346.pdf [firstpage_image] =>[orig_patent_app_number] => 11076970 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/076970
Selecting a bias for a level shifting device Mar 10, 2005 Issued
Array ( [id] => 462083 [patent_doc_number] => 07242238 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-10 [patent_title] => 'Drive circuit for voltage driven type semiconductor element' [patent_app_type] => utility [patent_app_number] => 11/077208 [patent_app_country] => US [patent_app_date] => 2005-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 6001 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/242/07242238.pdf [firstpage_image] =>[orig_patent_app_number] => 11077208 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/077208
Drive circuit for voltage driven type semiconductor element Mar 10, 2005 Issued
Array ( [id] => 496819 [patent_doc_number] => 07212043 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-01 [patent_title] => 'Line regulator with high bandwidth (BW) and high power supply rejection ration (PSRR) and wide range of output current' [patent_app_type] => utility [patent_app_number] => 11/078893 [patent_app_country] => US [patent_app_date] => 2005-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7274 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/212/07212043.pdf [firstpage_image] =>[orig_patent_app_number] => 11078893 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/078893
Line regulator with high bandwidth (BW) and high power supply rejection ration (PSRR) and wide range of output current Mar 10, 2005 Issued
Array ( [id] => 480836 [patent_doc_number] => 07224204 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-29 [patent_title] => 'Method and circuit for driving a gate of a MOS transistor negative' [patent_app_type] => utility [patent_app_number] => 11/073722 [patent_app_country] => US [patent_app_date] => 2005-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4335 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/224/07224204.pdf [firstpage_image] =>[orig_patent_app_number] => 11073722 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/073722
Method and circuit for driving a gate of a MOS transistor negative Mar 7, 2005 Issued
Array ( [id] => 638869 [patent_doc_number] => 07126407 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-24 [patent_title] => 'Method and device for generating a clock signal with predetermined clock signal properties' [patent_app_type] => utility [patent_app_number] => 11/074338 [patent_app_country] => US [patent_app_date] => 2005-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 9394 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/126/07126407.pdf [firstpage_image] =>[orig_patent_app_number] => 11074338 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/074338
Method and device for generating a clock signal with predetermined clock signal properties Mar 6, 2005 Issued
Array ( [id] => 677497 [patent_doc_number] => 07088162 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-08 [patent_title] => 'Circuit generating constant narrow-pulse-width bipolarity monocycles' [patent_app_type] => utility [patent_app_number] => 11/063889 [patent_app_country] => US [patent_app_date] => 2005-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 46 [patent_no_of_words] => 9491 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/088/07088162.pdf [firstpage_image] =>[orig_patent_app_number] => 11063889 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/063889
Circuit generating constant narrow-pulse-width bipolarity monocycles Feb 23, 2005 Issued
Array ( [id] => 770671 [patent_doc_number] => 07005899 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-02-28 [patent_title] => 'Frequency division/multiplication with jitter minimization' [patent_app_type] => utility [patent_app_number] => 11/062495 [patent_app_country] => US [patent_app_date] => 2005-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 3222 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/005/07005899.pdf [firstpage_image] =>[orig_patent_app_number] => 11062495 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/062495
Frequency division/multiplication with jitter minimization Feb 22, 2005 Issued
Array ( [id] => 7133572 [patent_doc_number] => 20050179482 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-18 [patent_title] => 'Systems, devices, and methods for providing control signals' [patent_app_type] => utility [patent_app_number] => 11/059073 [patent_app_country] => US [patent_app_date] => 2005-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3267 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0179/20050179482.pdf [firstpage_image] =>[orig_patent_app_number] => 11059073 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/059073
Systems, devices, and methods for providing control signals Feb 15, 2005 Issued
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