
An T. Luu
Examiner (ID: 5797, Phone: (571)272-1746 , Office: P/2842 )
| Most Active Art Unit | 2816 |
| Art Unit(s) | 2502, 2816, 2842 |
| Total Applications | 2105 |
| Issued Applications | 1967 |
| Pending Applications | 23 |
| Abandoned Applications | 118 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 477174
[patent_doc_number] => 07227395
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[patent_title] => 'High-performance memory interface circuit architecture'
[patent_app_type] => utility
[patent_app_number] => 11/055125
[patent_app_country] => US
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Array
(
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[patent_doc_number] => 07190201
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[patent_issue_date] => 2007-03-13
[patent_title] => 'Method and apparatus for initializing a delay locked loop'
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[firstpage_image] =>[orig_patent_app_number] => 11050644
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/050644 | Method and apparatus for initializing a delay locked loop | Feb 2, 2005 | Issued |
Array
(
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[patent_doc_number] => 20060170470
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[patent_kind] => A1
[patent_issue_date] => 2006-08-03
[patent_title] => 'CLOCK RECOVERING CIRCUIT UTILIZING A DELAY LOCKED LOOP FOR GENERATING AN OUTPUT CLOCK LOCKED TO AN ANALOG INPUT SIGNAL AND RELATED METHOD THEREOF'
[patent_app_type] => utility
[patent_app_number] => 10/906096
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/906096 | Clock recovering circuit utilizing a delay locked loop for generating an output clock locked to an analog input signal and related method thereof | Feb 2, 2005 | Issued |
Array
(
[id] => 7239306
[patent_doc_number] => 20050140421
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-06-30
[patent_title] => 'Level shifter and flat panel display'
[patent_app_type] => utility
[patent_app_number] => 11/040412
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[patent_app_date] => 2005-01-21
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[firstpage_image] =>[orig_patent_app_number] => 11040412
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/040412 | Level shifter and flat panel display | Jan 20, 2005 | Issued |
Array
(
[id] => 677480
[patent_doc_number] => 07088154
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[patent_kind] => B2
[patent_issue_date] => 2006-08-08
[patent_title] => 'Methods and arrangements for a low power phase-locked loop'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/037790 | Methods and arrangements for a low power phase-locked loop | Jan 17, 2005 | Issued |
Array
(
[id] => 7002951
[patent_doc_number] => 20050168264
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[patent_issue_date] => 2005-08-04
[patent_title] => 'Integrated circuit'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/035060 | Integrated circuit including an overvoltage protection circuit | Jan 13, 2005 | Issued |
Array
(
[id] => 562803
[patent_doc_number] => 07161417
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[patent_issue_date] => 2007-01-09
[patent_title] => 'Loop filter and method for generating stable control voltage of the same'
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[firstpage_image] =>[orig_patent_app_number] => 11034739
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/034739 | Loop filter and method for generating stable control voltage of the same | Jan 13, 2005 | Issued |
Array
(
[id] => 444089
[patent_doc_number] => 07256627
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2007-08-14
[patent_title] => 'Alignment of local transmit clock to synchronous data transfer clock having programmable transfer rate'
[patent_app_type] => utility
[patent_app_number] => 11/033755
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/033755 | Alignment of local transmit clock to synchronous data transfer clock having programmable transfer rate | Jan 12, 2005 | Issued |
Array
(
[id] => 7073099
[patent_doc_number] => 20050146365
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-07-07
[patent_title] => 'Apparatus for generating internal clock signal'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/031129 | Apparatus for generating internal clock signal | Jan 6, 2005 | Issued |
Array
(
[id] => 5629279
[patent_doc_number] => 20060145747
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-07-06
[patent_title] => 'Multi-stage charge pump voltage generator with protection of the devices of the charge pump'
[patent_app_type] => utility
[patent_app_number] => 11/028392
[patent_app_country] => US
[patent_app_date] => 2005-01-03
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/028392 | Multi-stage charge pump voltage generator with protection of the devices of the charge pump | Jan 2, 2005 | Issued |
Array
(
[id] => 798295
[patent_doc_number] => 07427885
[patent_country] => US
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[patent_issue_date] => 2008-09-23
[patent_title] => 'Semiconductor device having a power supply capacitor'
[patent_app_type] => utility
[patent_app_number] => 11/020169
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/020169 | Semiconductor device having a power supply capacitor | Dec 26, 2004 | Issued |
Array
(
[id] => 606936
[patent_doc_number] => 07154305
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[patent_title] => 'Periodic electrical signal frequency monitoring systems and methods'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/024332 | Periodic electrical signal frequency monitoring systems and methods | Dec 21, 2004 | Issued |
Array
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[id] => 646749
[patent_doc_number] => 07119596
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/021361 | Wide-range programmable delay line | Dec 21, 2004 | Issued |
Array
(
[id] => 5838930
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[patent_title] => 'Pulse-rejecting circuit for suppressing single-event transients'
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Array
(
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Array
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Array
(
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Array
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/988455 | Method and apparatus for generating non-skewed complementary signals through interpolation | Nov 11, 2004 | Issued |