Search

An T. Luu

Examiner (ID: 5797, Phone: (571)272-1746 , Office: P/2842 )

Most Active Art Unit
2816
Art Unit(s)
2502, 2816, 2842
Total Applications
2105
Issued Applications
1967
Pending Applications
23
Abandoned Applications
118

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 477174 [patent_doc_number] => 07227395 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-06-05 [patent_title] => 'High-performance memory interface circuit architecture' [patent_app_type] => utility [patent_app_number] => 11/055125 [patent_app_country] => US [patent_app_date] => 2005-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4040 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/227/07227395.pdf [firstpage_image] =>[orig_patent_app_number] => 11055125 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/055125
High-performance memory interface circuit architecture Feb 8, 2005 Issued
Array ( [id] => 523823 [patent_doc_number] => 07190201 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-13 [patent_title] => 'Method and apparatus for initializing a delay locked loop' [patent_app_type] => utility [patent_app_number] => 11/050644 [patent_app_country] => US [patent_app_date] => 2005-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 18 [patent_no_of_words] => 11922 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/190/07190201.pdf [firstpage_image] =>[orig_patent_app_number] => 11050644 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/050644
Method and apparatus for initializing a delay locked loop Feb 2, 2005 Issued
Array ( [id] => 5665120 [patent_doc_number] => 20060170470 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-03 [patent_title] => 'CLOCK RECOVERING CIRCUIT UTILIZING A DELAY LOCKED LOOP FOR GENERATING AN OUTPUT CLOCK LOCKED TO AN ANALOG INPUT SIGNAL AND RELATED METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 10/906096 [patent_app_country] => US [patent_app_date] => 2005-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3384 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0170/20060170470.pdf [firstpage_image] =>[orig_patent_app_number] => 10906096 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/906096
Clock recovering circuit utilizing a delay locked loop for generating an output clock locked to an analog input signal and related method thereof Feb 2, 2005 Issued
Array ( [id] => 7239306 [patent_doc_number] => 20050140421 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-30 [patent_title] => 'Level shifter and flat panel display' [patent_app_type] => utility [patent_app_number] => 11/040412 [patent_app_country] => US [patent_app_date] => 2005-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4836 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0140/20050140421.pdf [firstpage_image] =>[orig_patent_app_number] => 11040412 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/040412
Level shifter and flat panel display Jan 20, 2005 Issued
Array ( [id] => 677480 [patent_doc_number] => 07088154 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-08 [patent_title] => 'Methods and arrangements for a low power phase-locked loop' [patent_app_type] => utility [patent_app_number] => 11/037790 [patent_app_country] => US [patent_app_date] => 2005-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5013 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/088/07088154.pdf [firstpage_image] =>[orig_patent_app_number] => 11037790 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/037790
Methods and arrangements for a low power phase-locked loop Jan 17, 2005 Issued
Array ( [id] => 7002951 [patent_doc_number] => 20050168264 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-04 [patent_title] => 'Integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/035060 [patent_app_country] => US [patent_app_date] => 2005-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6579 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0168/20050168264.pdf [firstpage_image] =>[orig_patent_app_number] => 11035060 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/035060
Integrated circuit including an overvoltage protection circuit Jan 13, 2005 Issued
Array ( [id] => 562803 [patent_doc_number] => 07161417 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-01-09 [patent_title] => 'Loop filter and method for generating stable control voltage of the same' [patent_app_type] => utility [patent_app_number] => 11/034739 [patent_app_country] => US [patent_app_date] => 2005-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 4085 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/161/07161417.pdf [firstpage_image] =>[orig_patent_app_number] => 11034739 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/034739
Loop filter and method for generating stable control voltage of the same Jan 13, 2005 Issued
Array ( [id] => 444089 [patent_doc_number] => 07256627 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-08-14 [patent_title] => 'Alignment of local transmit clock to synchronous data transfer clock having programmable transfer rate' [patent_app_type] => utility [patent_app_number] => 11/033755 [patent_app_country] => US [patent_app_date] => 2005-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 7863 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/256/07256627.pdf [firstpage_image] =>[orig_patent_app_number] => 11033755 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/033755
Alignment of local transmit clock to synchronous data transfer clock having programmable transfer rate Jan 12, 2005 Issued
Array ( [id] => 7073099 [patent_doc_number] => 20050146365 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-07 [patent_title] => 'Apparatus for generating internal clock signal' [patent_app_type] => utility [patent_app_number] => 11/031129 [patent_app_country] => US [patent_app_date] => 2005-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3709 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0146/20050146365.pdf [firstpage_image] =>[orig_patent_app_number] => 11031129 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/031129
Apparatus for generating internal clock signal Jan 6, 2005 Issued
Array ( [id] => 5629279 [patent_doc_number] => 20060145747 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-06 [patent_title] => 'Multi-stage charge pump voltage generator with protection of the devices of the charge pump' [patent_app_type] => utility [patent_app_number] => 11/028392 [patent_app_country] => US [patent_app_date] => 2005-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3751 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0145/20060145747.pdf [firstpage_image] =>[orig_patent_app_number] => 11028392 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/028392
Multi-stage charge pump voltage generator with protection of the devices of the charge pump Jan 2, 2005 Issued
Array ( [id] => 798295 [patent_doc_number] => 07427885 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-09-23 [patent_title] => 'Semiconductor device having a power supply capacitor' [patent_app_type] => utility [patent_app_number] => 11/020169 [patent_app_country] => US [patent_app_date] => 2004-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 5309 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/427/07427885.pdf [firstpage_image] =>[orig_patent_app_number] => 11020169 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/020169
Semiconductor device having a power supply capacitor Dec 26, 2004 Issued
Array ( [id] => 606936 [patent_doc_number] => 07154305 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-12-26 [patent_title] => 'Periodic electrical signal frequency monitoring systems and methods' [patent_app_type] => utility [patent_app_number] => 11/024332 [patent_app_country] => US [patent_app_date] => 2004-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 10901 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/154/07154305.pdf [firstpage_image] =>[orig_patent_app_number] => 11024332 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/024332
Periodic electrical signal frequency monitoring systems and methods Dec 21, 2004 Issued
Array ( [id] => 646749 [patent_doc_number] => 07119596 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-10 [patent_title] => 'Wide-range programmable delay line' [patent_app_type] => utility [patent_app_number] => 11/021361 [patent_app_country] => US [patent_app_date] => 2004-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3338 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/119/07119596.pdf [firstpage_image] =>[orig_patent_app_number] => 11021361 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/021361
Wide-range programmable delay line Dec 21, 2004 Issued
Array ( [id] => 5838930 [patent_doc_number] => 20060119410 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-08 [patent_title] => 'Pulse-rejecting circuit for suppressing single-event transients' [patent_app_type] => utility [patent_app_number] => 11/005265 [patent_app_country] => US [patent_app_date] => 2004-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7715 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0119/20060119410.pdf [firstpage_image] =>[orig_patent_app_number] => 11005265 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/005265
Pulse-rejecting circuit for suppressing single-event transients Dec 5, 2004 Abandoned
Array ( [id] => 656212 [patent_doc_number] => 07109765 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-09-19 [patent_title] => 'Programmable phase shift circuitry' [patent_app_type] => utility [patent_app_number] => 10/996186 [patent_app_country] => US [patent_app_date] => 2004-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 25 [patent_no_of_words] => 9459 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/109/07109765.pdf [firstpage_image] =>[orig_patent_app_number] => 10996186 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/996186
Programmable phase shift circuitry Nov 21, 2004 Issued
Array ( [id] => 681532 [patent_doc_number] => 07084690 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-01 [patent_title] => 'Semiconductor integrated circuit device' [patent_app_type] => utility [patent_app_number] => 10/992730 [patent_app_country] => US [patent_app_date] => 2004-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 4544 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/084/07084690.pdf [firstpage_image] =>[orig_patent_app_number] => 10992730 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/992730
Semiconductor integrated circuit device Nov 21, 2004 Issued
Array ( [id] => 458340 [patent_doc_number] => 07245167 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-17 [patent_title] => 'Clock regulation apparatus and circuit arrangement' [patent_app_type] => utility [patent_app_number] => 10/989600 [patent_app_country] => US [patent_app_date] => 2004-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3810 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/245/07245167.pdf [firstpage_image] =>[orig_patent_app_number] => 10989600 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/989600
Clock regulation apparatus and circuit arrangement Nov 15, 2004 Issued
Array ( [id] => 461996 [patent_doc_number] => 07242224 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-07-10 [patent_title] => 'Continuous, wide-range frequency synthesis and phase tracking methods and apparatus' [patent_app_type] => utility [patent_app_number] => 10/990216 [patent_app_country] => US [patent_app_date] => 2004-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2381 [patent_no_of_claims] => 57 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/242/07242224.pdf [firstpage_image] =>[orig_patent_app_number] => 10990216 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/990216
Continuous, wide-range frequency synthesis and phase tracking methods and apparatus Nov 14, 2004 Issued
Array ( [id] => 692413 [patent_doc_number] => 07075346 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-07-11 [patent_title] => 'Synchronized frequency multiplier for multiple phase PWM control switching regulator without using a phase locked loop' [patent_app_type] => utility [patent_app_number] => 10/987107 [patent_app_country] => US [patent_app_date] => 2004-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3592 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/075/07075346.pdf [firstpage_image] =>[orig_patent_app_number] => 10987107 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/987107
Synchronized frequency multiplier for multiple phase PWM control switching regulator without using a phase locked loop Nov 11, 2004 Issued
Array ( [id] => 681531 [patent_doc_number] => 07084689 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-01 [patent_title] => 'Method and apparatus for generating non-skewed complementary signals through interpolation' [patent_app_type] => utility [patent_app_number] => 10/988455 [patent_app_country] => US [patent_app_date] => 2004-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 2650 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/084/07084689.pdf [firstpage_image] =>[orig_patent_app_number] => 10988455 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/988455
Method and apparatus for generating non-skewed complementary signals through interpolation Nov 11, 2004 Issued
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