
An T. Luu
Examiner (ID: 5797, Phone: (571)272-1746 , Office: P/2842 )
| Most Active Art Unit | 2816 |
| Art Unit(s) | 2502, 2816, 2842 |
| Total Applications | 2105 |
| Issued Applications | 1967 |
| Pending Applications | 23 |
| Abandoned Applications | 118 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 6903840
[patent_doc_number] => 20050099235
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-05-12
[patent_title] => 'PLL clock signal generation circuit'
[patent_app_type] => utility
[patent_app_number] => 10/983649
[patent_app_country] => US
[patent_app_date] => 2004-11-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 5360
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0099/20050099235.pdf
[firstpage_image] =>[orig_patent_app_number] => 10983649
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/983649 | PLL clock signal generation circuit | Nov 8, 2004 | Issued |
Array
(
[id] => 523811
[patent_doc_number] => 07190200
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-03-13
[patent_title] => 'Delay locked loop capable of performing reliable locking operation'
[patent_app_type] => utility
[patent_app_number] => 10/983504
[patent_app_country] => US
[patent_app_date] => 2004-11-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 5431
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/190/07190200.pdf
[firstpage_image] =>[orig_patent_app_number] => 10983504
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/983504 | Delay locked loop capable of performing reliable locking operation | Nov 7, 2004 | Issued |
Array
(
[id] => 5805574
[patent_doc_number] => 20060091927
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-05-04
[patent_title] => 'Delay stage for a digital delay line'
[patent_app_type] => utility
[patent_app_number] => 10/983045
[patent_app_country] => US
[patent_app_date] => 2004-11-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 1586
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0091/20060091927.pdf
[firstpage_image] =>[orig_patent_app_number] => 10983045
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/983045 | Delay stage for a digital delay line | Nov 2, 2004 | Abandoned |
Array
(
[id] => 6916032
[patent_doc_number] => 20050093593
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-05-05
[patent_title] => 'Clock generation system applicable to PLL'
[patent_app_type] => utility
[patent_app_number] => 10/973450
[patent_app_country] => US
[patent_app_date] => 2004-10-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 34
[patent_figures_cnt] => 34
[patent_no_of_words] => 15407
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0093/20050093593.pdf
[firstpage_image] =>[orig_patent_app_number] => 10973450
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/973450 | Clock generation system applicable to PLL | Oct 26, 2004 | Abandoned |
Array
(
[id] => 5741631
[patent_doc_number] => 20060087354
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-04-27
[patent_title] => 'Circuit having delay locked loop for correcting off chip driver duty distortion'
[patent_app_type] => utility
[patent_app_number] => 10/974521
[patent_app_country] => US
[patent_app_date] => 2004-10-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4981
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0087/20060087354.pdf
[firstpage_image] =>[orig_patent_app_number] => 10974521
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/974521 | Circuit having delay locked loop for correcting off chip driver duty distortion | Oct 26, 2004 | Issued |
Array
(
[id] => 6975921
[patent_doc_number] => 20050285636
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-12-29
[patent_title] => 'Clock switching circuit'
[patent_app_type] => utility
[patent_app_number] => 10/973258
[patent_app_country] => US
[patent_app_date] => 2004-10-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 6126
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0285/20050285636.pdf
[firstpage_image] =>[orig_patent_app_number] => 10973258
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/973258 | Clock switching circuit | Oct 26, 2004 | Issued |
Array
(
[id] => 5741630
[patent_doc_number] => 20060087353
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-04-27
[patent_title] => 'METHOD AND APPARATUS COMPENSATING FOR FREQUENCY DRIFT IN A DELAY LOCKED LOOP'
[patent_app_type] => utility
[patent_app_number] => 10/973389
[patent_app_country] => US
[patent_app_date] => 2004-10-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 6886
[patent_no_of_claims] => 40
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0087/20060087353.pdf
[firstpage_image] =>[orig_patent_app_number] => 10973389
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/973389 | Method and apparatus compensating for frequency drift in a delay locked loop | Oct 26, 2004 | Issued |
Array
(
[id] => 474482
[patent_doc_number] => 07230461
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2007-06-12
[patent_title] => 'Retiming circuits for phase-locked loops'
[patent_app_type] => utility
[patent_app_number] => 10/973757
[patent_app_country] => US
[patent_app_date] => 2004-10-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 3311
[patent_no_of_claims] => 56
[patent_no_of_ind_claims] => 10
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/230/07230461.pdf
[firstpage_image] =>[orig_patent_app_number] => 10973757
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/973757 | Retiming circuits for phase-locked loops | Oct 25, 2004 | Issued |
Array
(
[id] => 638865
[patent_doc_number] => 07126404
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2006-10-24
[patent_title] => 'High resolution digital delay circuit for PLL and DLL'
[patent_app_type] => utility
[patent_app_number] => 10/973963
[patent_app_country] => US
[patent_app_date] => 2004-10-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 5282
[patent_no_of_claims] => 42
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 130
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/126/07126404.pdf
[firstpage_image] =>[orig_patent_app_number] => 10973963
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/973963 | High resolution digital delay circuit for PLL and DLL | Oct 24, 2004 | Issued |
Array
(
[id] => 5137535
[patent_doc_number] => 20070079164
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-04-05
[patent_title] => 'Frequency divider and an electronic device incorporating such a frequency divider'
[patent_app_type] => utility
[patent_app_number] => 10/575958
[patent_app_country] => US
[patent_app_date] => 2004-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 2675
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0079/20070079164.pdf
[firstpage_image] =>[orig_patent_app_number] => 10575958
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/575958 | Frequency divider and an electronic device incorporating such a frequency divider | Sep 23, 2004 | Issued |
Array
(
[id] => 770670
[patent_doc_number] => 07005898
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-02-28
[patent_title] => 'Programmable divider with built-in programmable delay chain for high-speed/low power application'
[patent_app_type] => utility
[patent_app_number] => 10/946172
[patent_app_country] => US
[patent_app_date] => 2004-09-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 5194
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 170
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/005/07005898.pdf
[firstpage_image] =>[orig_patent_app_number] => 10946172
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/946172 | Programmable divider with built-in programmable delay chain for high-speed/low power application | Sep 21, 2004 | Issued |
Array
(
[id] => 492314
[patent_doc_number] => 07215166
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-05-08
[patent_title] => 'DLL circuit with delay equal to one clock cycle'
[patent_app_type] => utility
[patent_app_number] => 10/942129
[patent_app_country] => US
[patent_app_date] => 2004-09-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 5276
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 122
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/215/07215166.pdf
[firstpage_image] =>[orig_patent_app_number] => 10942129
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/942129 | DLL circuit with delay equal to one clock cycle | Sep 15, 2004 | Issued |
Array
(
[id] => 7125544
[patent_doc_number] => 20050057288
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-03-17
[patent_title] => 'Semiconductor device with pump circuit'
[patent_app_type] => utility
[patent_app_number] => 10/941004
[patent_app_country] => US
[patent_app_date] => 2004-09-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 21
[patent_no_of_words] => 16817
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0057/20050057288.pdf
[firstpage_image] =>[orig_patent_app_number] => 10941004
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/941004 | Semiconductor device with pump circuit | Sep 14, 2004 | Issued |
Array
(
[id] => 496873
[patent_doc_number] => 07212052
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-05-01
[patent_title] => 'Jitter suppressing delay locked loop circuits and related methods'
[patent_app_type] => utility
[patent_app_number] => 10/925522
[patent_app_country] => US
[patent_app_date] => 2004-08-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 3057
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/212/07212052.pdf
[firstpage_image] =>[orig_patent_app_number] => 10925522
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/925522 | Jitter suppressing delay locked loop circuits and related methods | Aug 24, 2004 | Issued |
Array
(
[id] => 6956204
[patent_doc_number] => 20050212574
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-09-29
[patent_title] => 'Digital DLL device, digital DLL control method, and digital DLL control program'
[patent_app_type] => utility
[patent_app_number] => 10/921216
[patent_app_country] => US
[patent_app_date] => 2004-08-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5811
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0212/20050212574.pdf
[firstpage_image] =>[orig_patent_app_number] => 10921216
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/921216 | Digital DLL device, digital DLL control method, and digital DLL control program | Aug 18, 2004 | Issued |
Array
(
[id] => 7243981
[patent_doc_number] => 20050073344
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-04-07
[patent_title] => 'Semiconductor device, receiver circuit, and frequency multiplier circuit'
[patent_app_type] => utility
[patent_app_number] => 10/922381
[patent_app_country] => US
[patent_app_date] => 2004-08-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 19
[patent_no_of_words] => 10065
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0073/20050073344.pdf
[firstpage_image] =>[orig_patent_app_number] => 10922381
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/922381 | Semiconductor device, receiver circuit, and frequency multiplier circuit | Aug 18, 2004 | Issued |
Array
(
[id] => 5589145
[patent_doc_number] => 20060038596
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-02-23
[patent_title] => 'Delay locked loop circuitry and method for optimizing delay timing in mixed signal systems'
[patent_app_type] => utility
[patent_app_number] => 10/921001
[patent_app_country] => US
[patent_app_date] => 2004-08-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 5240
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0038/20060038596.pdf
[firstpage_image] =>[orig_patent_app_number] => 10921001
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/921001 | Delay locked loop circuitry and method for optimizing delay timing in mixed signal systems | Aug 17, 2004 | Abandoned |
Array
(
[id] => 7023381
[patent_doc_number] => 20050017775
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-01-27
[patent_title] => 'PLL/DLL circuitry programmable for high bandwidth and low bandwidth applications'
[patent_app_type] => utility
[patent_app_number] => 10/921453
[patent_app_country] => US
[patent_app_date] => 2004-08-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 8191
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0017/20050017775.pdf
[firstpage_image] =>[orig_patent_app_number] => 10921453
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/921453 | PLL/DLL circuitry programmable for high bandwidth and low bandwidth applications | Aug 17, 2004 | Issued |
Array
(
[id] => 664460
[patent_doc_number] => 07102391
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2006-09-05
[patent_title] => 'Clock-generator architecture for a programmable-logic-based system on a chip'
[patent_app_type] => utility
[patent_app_number] => 10/903473
[patent_app_country] => US
[patent_app_date] => 2004-07-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 20
[patent_no_of_words] => 15593
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/102/07102391.pdf
[firstpage_image] =>[orig_patent_app_number] => 10903473
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/903473 | Clock-generator architecture for a programmable-logic-based system on a chip | Jul 28, 2004 | Issued |
Array
(
[id] => 703598
[patent_doc_number] => 07064591
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2006-06-20
[patent_title] => 'Coarse tuning for fractional-N synthesizers'
[patent_app_type] => utility
[patent_app_number] => 10/901669
[patent_app_country] => US
[patent_app_date] => 2004-07-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 9
[patent_no_of_words] => 5081
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/064/07064591.pdf
[firstpage_image] =>[orig_patent_app_number] => 10901669
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/901669 | Coarse tuning for fractional-N synthesizers | Jul 28, 2004 | Issued |