An T. Luu

Array ( [id] => 589236 [patent_doc_number] => 07446587 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-04 [patent_title] => 'Semiconductor device and driving method thereof' [patent_app_type] => utility [patent_app_number] => 10/900141 [patent_app_country] => US [patent_app_date] => 2004-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6969 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/446/07446587.pdf [firstpage_image] =>[orig_patent_app_number] => 10900141 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 700787 [patent_doc_number] => 07068111 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-27 [patent_title] => 'PLL having a multi-level voltage-current converter and a method for locking a clock phase using multi-level voltage-current conversion' [patent_app_type] => utility [patent_app_number] => 10/894409 [patent_app_country] => US [patent_app_date] => 2004-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4949 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/068/07068111.pdf [firstpage_image] =>[orig_patent_app_number] => 10894409 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7618351 [patent_doc_number] => 06944842 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-09-13 [patent_title] => 'Method for making large-scale ASIC using pre-engineered long distance routing structure' [patent_app_type] => utility [patent_app_number] => 10/894559 [patent_app_country] => US [patent_app_date] => 2004-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 6523 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/944/06944842.pdf [firstpage_image] =>[orig_patent_app_number] => 10894559 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 997053 [patent_doc_number] => 06914469 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-07-05 [patent_title] => 'Clock divider circuit' [patent_app_type] => utility [patent_app_number] => 10/892802 [patent_app_country] => US [patent_app_date] => 2004-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3900 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/914/06914469.pdf [firstpage_image] =>[orig_patent_app_number] => 10892802 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7621964 [patent_doc_number] => 06977537 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-12-20 [patent_title] => 'Low gain phase-locked loop circuit' [patent_app_type] => utility [patent_app_number] => 10/890332 [patent_app_country] => US [patent_app_date] => 2004-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 2980 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/977/06977537.pdf [firstpage_image] =>[orig_patent_app_number] => 10890332 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1044510 [patent_doc_number] => 06867637 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-03-15 [patent_title] => 'Semiconductor integrated circuit device including a substrate bias controller and a current limiting circuit' [patent_app_type] => utility [patent_app_number] => 10/889141 [patent_app_country] => US [patent_app_date] => 2004-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 85 [patent_no_of_words] => 28629 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/867/06867637.pdf [firstpage_image] =>[orig_patent_app_number] => 10889141 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7339784 [patent_doc_number] => 20040246053 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-09 [patent_title] => 'Highly linear variable gain amplifier' [patent_app_type] => new [patent_app_number] => 10/890421 [patent_app_country] => US [patent_app_date] => 2004-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5276 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0246/20040246053.pdf [firstpage_image] =>[orig_patent_app_number] => 10890421 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 760212 [patent_doc_number] => 07015764 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-21 [patent_title] => 'Analog implementation of spread spectrum frequency modulation in a programmable phase locked loop (PLL) system' [patent_app_type] => utility [patent_app_number] => 10/888549 [patent_app_country] => US [patent_app_date] => 2004-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5279 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/015/07015764.pdf [firstpage_image] =>[orig_patent_app_number] => 10888549 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7252352 [patent_doc_number] => 20040239428 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-02 [patent_title] => 'Active protection circuit for load mismatched power amplifier' [patent_app_type] => new [patent_app_number] => 10/884135 [patent_app_country] => US [patent_app_date] => 2004-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2060 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 3 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0239/20040239428.pdf [firstpage_image] =>[orig_patent_app_number] => 10884135 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6916035 [patent_doc_number] => 20050093596 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-05 [patent_title] => 'Power supply apparatus for delay locked loop and method thereof' [patent_app_type] => utility [patent_app_number] => 10/877601 [patent_app_country] => US [patent_app_date] => 2004-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2279 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0093/20050093596.pdf [firstpage_image] =>[orig_patent_app_number] => 10877601 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7274291 [patent_doc_number] => 20040233742 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-25 [patent_title] => 'Apparatus and method for adusting clock skew' [patent_app_type] => new [patent_app_number] => 10/870138 [patent_app_country] => US [patent_app_date] => 2004-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4601 [patent_no_of_claims] => 79 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0233/20040233742.pdf [firstpage_image] =>[orig_patent_app_number] => 10870138 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7238434 [patent_doc_number] => 20040257128 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-23 [patent_title] => 'Low-power and low-noise comparator having inverter with decreased peak current' [patent_app_type] => new [patent_app_number] => 10/870313 [patent_app_country] => US [patent_app_date] => 2004-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5819 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0257/20040257128.pdf [firstpage_image] =>[orig_patent_app_number] => 10870313 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 857742 [patent_doc_number] => 07375568 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-05-20 [patent_title] => 'Logic circuit with restrained leak current to differential circuit' [patent_app_type] => utility [patent_app_number] => 10/560930 [patent_app_country] => US [patent_app_date] => 2004-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 22 [patent_no_of_words] => 8483 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/375/07375568.pdf [firstpage_image] =>[orig_patent_app_number] => 10560930 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 735167 [patent_doc_number] => 07038518 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-05-02 [patent_title] => 'Method and apparatus for adjusting the phase and frequency of a periodic wave' [patent_app_type] => utility [patent_app_number] => 10/869479 [patent_app_country] => US [patent_app_date] => 2004-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 26 [patent_no_of_words] => 7133 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/038/07038518.pdf [firstpage_image] =>[orig_patent_app_number] => 10869479 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7054268 [patent_doc_number] => 20050275440 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-15 [patent_title] => 'Technique for operating a delay circuit' [patent_app_type] => utility [patent_app_number] => 10/865780 [patent_app_country] => US [patent_app_date] => 2004-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2927 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0275/20050275440.pdf [firstpage_image] =>[orig_patent_app_number] => 10865780 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 721809 [patent_doc_number] => 07049878 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-23 [patent_title] => 'Down-converter using an on-chip bias circuit for enhancing symmetry and linearity and testing device thereof' [patent_app_type] => utility [patent_app_number] => 10/860223 [patent_app_country] => US [patent_app_date] => 2004-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4225 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/049/07049878.pdf [firstpage_image] =>[orig_patent_app_number] => 10860223 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7364654 [patent_doc_number] => 20040217802 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-04 [patent_title] => 'Semiconductor device' [patent_app_type] => new [patent_app_number] => 10/851156 [patent_app_country] => US [patent_app_date] => 2004-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 8069 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 3 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0217/20040217802.pdf [firstpage_image] =>[orig_patent_app_number] => 10851156 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 656213 [patent_doc_number] => 07109766 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-19 [patent_title] => 'Adjustable frequency delay-locked loop' [patent_app_type] => utility [patent_app_number] => 10/830337 [patent_app_country] => US [patent_app_date] => 2004-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 7064 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/109/07109766.pdf [firstpage_image] =>[orig_patent_app_number] => 10830337 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 791015 [patent_doc_number] => 06985040 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-10 [patent_title] => 'Voltage controlled oscillator and method of generating an oscillating signal' [patent_app_type] => utility [patent_app_number] => 10/829134 [patent_app_country] => US [patent_app_date] => 2004-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4145 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/985/06985040.pdf [firstpage_image] =>[orig_patent_app_number] => 10829134 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7238401 [patent_doc_number] => 20040257122 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-23 [patent_title] => 'Clock signal detection circuit and semiconductor integrated circuit using the same' [patent_app_type] => new [patent_app_number] => 10/829100 [patent_app_country] => US [patent_app_date] => 2004-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3795 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0257/20040257122.pdf [firstpage_image] =>[orig_patent_app_number] => 10829100 [rel_patent_id] =>[rel_patent_doc_number] =>)