
An T. Luu
Examiner (ID: 5797, Phone: (571)272-1746 , Office: P/2842 )
| Most Active Art Unit | 2816 |
| Art Unit(s) | 2502, 2816, 2842 |
| Total Applications | 2105 |
| Issued Applications | 1967 |
| Pending Applications | 23 |
| Abandoned Applications | 118 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 6964347
[patent_doc_number] => 20050231244
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[patent_issue_date] => 2005-10-20
[patent_title] => 'Mothod and apparatus for ensuring synchronization of clocks in a multiple clock system'
[patent_app_type] => utility
[patent_app_number] => 10/825191
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/825191 | Method and apparatus for ensuring synchronization of clocks in a multiple clock system | Apr 14, 2004 | Issued |
Array
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[patent_issue_date] => 2005-01-11
[patent_title] => 'Muxed-output double-date-rate-2 (DDR2) register with fast propagation delay'
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Array
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[patent_issue_date] => 2006-03-07
[patent_title] => 'Pulsewidth control loop device with complementary signals'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/820766 | Pulsewidth control loop device with complementary signals | Apr 8, 2004 | Issued |
Array
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[patent_issue_date] => 2006-09-05
[patent_title] => 'Phase detector, clock distribution circuit, and LSI'
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Array
(
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[patent_title] => 'High bandwidth phase locked loop (PLL)'
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Array
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Array
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[patent_title] => 'Phase difference detector, particularly for a PLL circuit'
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Array
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[patent_title] => 'Method and apparatus for fractional RF signal synthesis'
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Array
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[patent_title] => 'Systems and methods for providing distributed control signal redundancy among electronic circuits'
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Array
(
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[patent_title] => 'Clock frequency monitor'
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Array
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Array
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Array
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Array
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Array
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Array
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Array
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Array
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Array
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