Search

An T. Luu

Examiner (ID: 5797, Phone: (571)272-1746 , Office: P/2842 )

Most Active Art Unit
2816
Art Unit(s)
2502, 2816, 2842
Total Applications
2105
Issued Applications
1967
Pending Applications
23
Abandoned Applications
118

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6964347 [patent_doc_number] => 20050231244 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-20 [patent_title] => 'Mothod and apparatus for ensuring synchronization of clocks in a multiple clock system' [patent_app_type] => utility [patent_app_number] => 10/825191 [patent_app_country] => US [patent_app_date] => 2004-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4608 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0231/20050231244.pdf [firstpage_image] =>[orig_patent_app_number] => 10825191 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/825191
Method and apparatus for ensuring synchronization of clocks in a multiple clock system Apr 14, 2004 Issued
Array ( [id] => 7610799 [patent_doc_number] => 06842059 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-01-11 [patent_title] => 'Muxed-output double-date-rate-2 (DDR2) register with fast propagation delay' [patent_app_type] => utility [patent_app_number] => 10/709132 [patent_app_country] => US [patent_app_date] => 2004-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3987 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 342 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/842/06842059.pdf [firstpage_image] =>[orig_patent_app_number] => 10709132 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/709132
Muxed-output double-date-rate-2 (DDR2) register with fast propagation delay Apr 14, 2004 Issued
Array ( [id] => 767564 [patent_doc_number] => 07009436 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-07 [patent_title] => 'Pulsewidth control loop device with complementary signals' [patent_app_type] => utility [patent_app_number] => 10/820766 [patent_app_country] => US [patent_app_date] => 2004-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3093 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/009/07009436.pdf [firstpage_image] =>[orig_patent_app_number] => 10820766 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/820766
Pulsewidth control loop device with complementary signals Apr 8, 2004 Issued
Array ( [id] => 664483 [patent_doc_number] => 07102406 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-05 [patent_title] => 'Phase detector, clock distribution circuit, and LSI' [patent_app_type] => utility [patent_app_number] => 10/816808 [patent_app_country] => US [patent_app_date] => 2004-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 6864 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/102/07102406.pdf [firstpage_image] =>[orig_patent_app_number] => 10816808 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/816808
Phase detector, clock distribution circuit, and LSI Apr 4, 2004 Issued
Array ( [id] => 7604787 [patent_doc_number] => 07116144 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-10-03 [patent_title] => 'High bandwidth phase locked loop (PLL)' [patent_app_type] => utility [patent_app_number] => 10/802597 [patent_app_country] => US [patent_app_date] => 2004-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 4569 [patent_no_of_claims] => 55 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/116/07116144.pdf [firstpage_image] =>[orig_patent_app_number] => 10802597 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/802597
High bandwidth phase locked loop (PLL) Mar 15, 2004 Issued
Array ( [id] => 717739 [patent_doc_number] => 07053719 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-30 [patent_title] => 'Controlling a voltage controlled oscillator in a bang-bang phase locked loop' [patent_app_type] => utility [patent_app_number] => 10/797964 [patent_app_country] => US [patent_app_date] => 2004-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 6990 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/053/07053719.pdf [firstpage_image] =>[orig_patent_app_number] => 10797964 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/797964
Controlling a voltage controlled oscillator in a bang-bang phase locked loop Mar 10, 2004 Issued
Array ( [id] => 7273496 [patent_doc_number] => 20040232947 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-25 [patent_title] => 'Phase difference detector, particularly for a PLL circuit' [patent_app_type] => new [patent_app_number] => 10/797621 [patent_app_country] => US [patent_app_date] => 2004-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5146 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0232/20040232947.pdf [firstpage_image] =>[orig_patent_app_number] => 10797621 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/797621
Phase difference detector, particularly for a PLL circuit Mar 9, 2004 Issued
Array ( [id] => 7155559 [patent_doc_number] => 20050083085 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-21 [patent_title] => 'Method and apparatus for fractional RF signal synthesis' [patent_app_type] => utility [patent_app_number] => 10/796417 [patent_app_country] => US [patent_app_date] => 2004-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4259 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20050083085.pdf [firstpage_image] =>[orig_patent_app_number] => 10796417 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/796417
Method and apparatus for fractional RF signal synthesis Mar 9, 2004 Issued
Array ( [id] => 474492 [patent_doc_number] => 07230468 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-06-12 [patent_title] => 'Systems and methods for providing distributed control signal redundancy among electronic circuits' [patent_app_type] => utility [patent_app_number] => 10/797776 [patent_app_country] => US [patent_app_date] => 2004-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 1574 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/230/07230468.pdf [firstpage_image] =>[orig_patent_app_number] => 10797776 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/797776
Systems and methods for providing distributed control signal redundancy among electronic circuits Mar 9, 2004 Issued
Array ( [id] => 461992 [patent_doc_number] => 07242223 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-07-10 [patent_title] => 'Clock frequency monitor' [patent_app_type] => utility [patent_app_number] => 10/797478 [patent_app_country] => US [patent_app_date] => 2004-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 4588 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/242/07242223.pdf [firstpage_image] =>[orig_patent_app_number] => 10797478 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/797478
Clock frequency monitor Mar 9, 2004 Issued
Array ( [id] => 405138 [patent_doc_number] => 07288972 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-10-30 [patent_title] => 'Circuitry for synthesizing an arbitrary clock signal and methods for the synthesis thereof' [patent_app_type] => utility [patent_app_number] => 10/796496 [patent_app_country] => US [patent_app_date] => 2004-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4799 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/288/07288972.pdf [firstpage_image] =>[orig_patent_app_number] => 10796496 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/796496
Circuitry for synthesizing an arbitrary clock signal and methods for the synthesis thereof Mar 7, 2004 Issued
Array ( [id] => 1006414 [patent_doc_number] => 06906572 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-06-14 [patent_title] => 'Semiconductor integrated circuit device' [patent_app_type] => utility [patent_app_number] => 10/792720 [patent_app_country] => US [patent_app_date] => 2004-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 4500 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/906/06906572.pdf [firstpage_image] =>[orig_patent_app_number] => 10792720 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/792720
Semiconductor integrated circuit device Mar 4, 2004 Issued
Array ( [id] => 6942955 [patent_doc_number] => 20050195003 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-08 [patent_title] => 'Charge pump circuit using active feedback controlled current sources' [patent_app_type] => utility [patent_app_number] => 10/794189 [patent_app_country] => US [patent_app_date] => 2004-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2890 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0195/20050195003.pdf [firstpage_image] =>[orig_patent_app_number] => 10794189 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/794189
Charge pump circuit using active feedback controlled current sources Mar 4, 2004 Issued
Array ( [id] => 7144790 [patent_doc_number] => 20040169564 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-02 [patent_title] => 'Voltage-controlled oscillator' [patent_app_type] => new [patent_app_number] => 10/787129 [patent_app_country] => US [patent_app_date] => 2004-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7797 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0169/20040169564.pdf [firstpage_image] =>[orig_patent_app_number] => 10787129 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/787129
Voltage-controlled oscillator Feb 26, 2004 Abandoned
Array ( [id] => 7048882 [patent_doc_number] => 20050184769 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-25 [patent_title] => 'Synchronization of signals' [patent_app_type] => utility [patent_app_number] => 10/787841 [patent_app_country] => US [patent_app_date] => 2004-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4724 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0184/20050184769.pdf [firstpage_image] =>[orig_patent_app_number] => 10787841 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/787841
Synchronization of signals Feb 24, 2004 Issued
Array ( [id] => 7048885 [patent_doc_number] => 20050184772 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-25 [patent_title] => 'POWERUP CONTROL OF PLL' [patent_app_type] => utility [patent_app_number] => 10/786584 [patent_app_country] => US [patent_app_date] => 2004-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7181 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0184/20050184772.pdf [firstpage_image] =>[orig_patent_app_number] => 10786584 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/786584
Powerup control of PLL Feb 24, 2004 Issued
Array ( [id] => 979513 [patent_doc_number] => 06930519 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-16 [patent_title] => 'Frequency division/multiplication with jitter minimization' [patent_app_type] => utility [patent_app_number] => 10/782890 [patent_app_country] => US [patent_app_date] => 2004-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 3200 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/930/06930519.pdf [firstpage_image] =>[orig_patent_app_number] => 10782890 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/782890
Frequency division/multiplication with jitter minimization Feb 22, 2004 Issued
Array ( [id] => 5660132 [patent_doc_number] => 20060250728 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-09 [patent_title] => 'Multiple phase simultaneous switching preventing circuit, pwm inverter and its driving method' [patent_app_type] => utility [patent_app_number] => 10/558688 [patent_app_country] => US [patent_app_date] => 2004-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 18685 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0250/20060250728.pdf [firstpage_image] =>[orig_patent_app_number] => 10558688 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/558688
Multiple phase simultaneous switching preventing circuit, PWM inverter and its driving method Feb 18, 2004 Issued
Array ( [id] => 7023387 [patent_doc_number] => 20050017781 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-27 [patent_title] => 'Complementary signal generator' [patent_app_type] => utility [patent_app_number] => 10/779649 [patent_app_country] => US [patent_app_date] => 2004-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5592 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0017/20050017781.pdf [firstpage_image] =>[orig_patent_app_number] => 10779649 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/779649
Complementary signal generator Feb 17, 2004 Issued
Array ( [id] => 896608 [patent_doc_number] => 07342432 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-03-11 [patent_title] => 'Mixer circuit having improved linearity and noise figure' [patent_app_type] => utility [patent_app_number] => 10/775234 [patent_app_country] => US [patent_app_date] => 2004-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6233 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/342/07342432.pdf [firstpage_image] =>[orig_patent_app_number] => 10775234 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/775234
Mixer circuit having improved linearity and noise figure Feb 10, 2004 Issued
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