
An T. Luu
Examiner (ID: 5797, Phone: (571)272-1746 , Office: P/2842 )
| Most Active Art Unit | 2816 |
| Art Unit(s) | 2502, 2816, 2842 |
| Total Applications | 2105 |
| Issued Applications | 1967 |
| Pending Applications | 23 |
| Abandoned Applications | 118 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 775105
[patent_doc_number] => 07002380
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-02-21
[patent_title] => 'Frequency divider with funnel structure'
[patent_app_type] => utility
[patent_app_number] => 10/772584
[patent_app_country] => US
[patent_app_date] => 2004-02-06
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[pdf_file] => patents/07/002/07002380.pdf
[firstpage_image] =>[orig_patent_app_number] => 10772584
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/772584 | Frequency divider with funnel structure | Feb 5, 2004 | Issued |
Array
(
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[patent_doc_number] => 20050068073
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-03-31
[patent_title] => 'Regulated adaptive-bandwidth PLL/DLL using self-biasing current from a VCO/VCDL'
[patent_app_type] => utility
[patent_app_number] => 10/770435
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Array
(
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[patent_doc_number] => 20050168258
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[patent_kind] => A1
[patent_issue_date] => 2005-08-04
[patent_title] => 'Method and apparatus for creating variable delay'
[patent_app_type] => utility
[patent_app_number] => 10/771124
[patent_app_country] => US
[patent_app_date] => 2004-02-02
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/771124 | Method and apparatus for creating variable delay | Feb 1, 2004 | Abandoned |
Array
(
[id] => 7002947
[patent_doc_number] => 20050168260
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-08-04
[patent_title] => 'Configurable delay line circuit'
[patent_app_type] => utility
[patent_app_number] => 10/767088
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[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/767088 | Configurable delay line circuit | Jan 28, 2004 | Abandoned |
Array
(
[id] => 7409612
[patent_doc_number] => 20040227548
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[patent_kind] => A1
[patent_issue_date] => 2004-11-18
[patent_title] => 'Apparatus for generating clock signal in optical disk and method thereof'
[patent_app_type] => new
[patent_app_number] => 10/765183
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/765183 | Apparatus for generating clock signal in optical disk and method thereof | Jan 27, 2004 | Issued |
Array
(
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[patent_title] => 'Programmable dual-edge triggered counter'
[patent_app_type] => new
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/765766 | Programmable dual-edge triggered counter | Jan 25, 2004 | Issued |
Array
(
[id] => 683262
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[patent_issue_date] => 2006-07-25
[patent_title] => 'Semiconductor integrated circuit related to a circuit operating on the basis of a clock signal'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/760475 | Semiconductor integrated circuit related to a circuit operating on the basis of a clock signal | Jan 20, 2004 | Issued |
Array
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[patent_title] => 'Clock-synchronized serial communication device and semiconductor integrated circuit device'
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Array
(
[id] => 1006384
[patent_doc_number] => 06906560
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[patent_title] => 'Phase-continuous frequency synthesizer'
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[patent_app_number] => 10/760990
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[firstpage_image] =>[orig_patent_app_number] => 10760990
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/760990 | Phase-continuous frequency synthesizer | Jan 19, 2004 | Issued |
Array
(
[id] => 7037206
[patent_doc_number] => 20050156640
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-07-21
[patent_title] => 'Novel charge leakage correction circuit for applications in PLLs'
[patent_app_type] => utility
[patent_app_number] => 10/759942
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[patent_app_date] => 2004-01-16
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/759942 | Charge leakage correction circuit for applications in PLLs | Jan 15, 2004 | Issued |
Array
(
[id] => 775111
[patent_doc_number] => 07002385
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-02-21
[patent_title] => 'Circuit arrangement and method for producing a pulse width modulated signal'
[patent_app_type] => utility
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[firstpage_image] =>[orig_patent_app_number] => 10753508
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/753508 | Circuit arrangement and method for producing a pulse width modulated signal | Jan 7, 2004 | Issued |
Array
(
[id] => 7175894
[patent_doc_number] => 20040201408
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Array
(
[id] => 935824
[patent_doc_number] => 06975174
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Array
(
[id] => 7621960
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[patent_issue_date] => 2005-12-20
[patent_title] => 'Variable time constant circuit and filter circuit using the same'
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Array
(
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Array
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Array
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Array
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/741149 | Memory clock slowdown | Dec 17, 2003 | Issued |