Search

An T. Luu

Examiner (ID: 5797, Phone: (571)272-1746 , Office: P/2842 )

Most Active Art Unit
2816
Art Unit(s)
2502, 2816, 2842
Total Applications
2105
Issued Applications
1967
Pending Applications
23
Abandoned Applications
118

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 775105 [patent_doc_number] => 07002380 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-02-21 [patent_title] => 'Frequency divider with funnel structure' [patent_app_type] => utility [patent_app_number] => 10/772584 [patent_app_country] => US [patent_app_date] => 2004-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 6376 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/002/07002380.pdf [firstpage_image] =>[orig_patent_app_number] => 10772584 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/772584
Frequency divider with funnel structure Feb 5, 2004 Issued
Array ( [id] => 7114772 [patent_doc_number] => 20050068073 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-31 [patent_title] => 'Regulated adaptive-bandwidth PLL/DLL using self-biasing current from a VCO/VCDL' [patent_app_type] => utility [patent_app_number] => 10/770435 [patent_app_country] => US [patent_app_date] => 2004-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4044 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0068/20050068073.pdf [firstpage_image] =>[orig_patent_app_number] => 10770435 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/770435
Regulated adaptive-bandwidth PLL/DLL using self-biasing current from a VCO/VCDL Feb 2, 2004 Abandoned
Array ( [id] => 7002945 [patent_doc_number] => 20050168258 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-04 [patent_title] => 'Method and apparatus for creating variable delay' [patent_app_type] => utility [patent_app_number] => 10/771124 [patent_app_country] => US [patent_app_date] => 2004-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5429 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0168/20050168258.pdf [firstpage_image] =>[orig_patent_app_number] => 10771124 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/771124
Method and apparatus for creating variable delay Feb 1, 2004 Abandoned
Array ( [id] => 7002947 [patent_doc_number] => 20050168260 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-04 [patent_title] => 'Configurable delay line circuit' [patent_app_type] => utility [patent_app_number] => 10/767088 [patent_app_country] => US [patent_app_date] => 2004-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3726 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0168/20050168260.pdf [firstpage_image] =>[orig_patent_app_number] => 10767088 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/767088
Configurable delay line circuit Jan 28, 2004 Abandoned
Array ( [id] => 7409612 [patent_doc_number] => 20040227548 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-18 [patent_title] => 'Apparatus for generating clock signal in optical disk and method thereof' [patent_app_type] => new [patent_app_number] => 10/765183 [patent_app_country] => US [patent_app_date] => 2004-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3734 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0227/20040227548.pdf [firstpage_image] =>[orig_patent_app_number] => 10765183 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/765183
Apparatus for generating clock signal in optical disk and method thereof Jan 27, 2004 Issued
Array ( [id] => 7408311 [patent_doc_number] => 20040263221 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-30 [patent_title] => 'Programmable dual-edge triggered counter' [patent_app_type] => new [patent_app_number] => 10/765766 [patent_app_country] => US [patent_app_date] => 2004-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8026 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0263/20040263221.pdf [firstpage_image] =>[orig_patent_app_number] => 10765766 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/765766
Programmable dual-edge triggered counter Jan 25, 2004 Issued
Array ( [id] => 683262 [patent_doc_number] => 07081778 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-07-25 [patent_title] => 'Semiconductor integrated circuit related to a circuit operating on the basis of a clock signal' [patent_app_type] => utility [patent_app_number] => 10/760475 [patent_app_country] => US [patent_app_date] => 2004-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4941 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/081/07081778.pdf [firstpage_image] =>[orig_patent_app_number] => 10760475 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/760475
Semiconductor integrated circuit related to a circuit operating on the basis of a clock signal Jan 20, 2004 Issued
Array ( [id] => 7459501 [patent_doc_number] => 20040165688 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-26 [patent_title] => 'Clock-synchronized serial communication device and semiconductor integrated circuit device' [patent_app_type] => new [patent_app_number] => 10/760349 [patent_app_country] => US [patent_app_date] => 2004-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5553 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0165/20040165688.pdf [firstpage_image] =>[orig_patent_app_number] => 10760349 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/760349
Clock-synchronized serial communication device and semiconductor integrated circuit device Jan 20, 2004 Issued
Array ( [id] => 1006384 [patent_doc_number] => 06906560 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-06-14 [patent_title] => 'Phase-continuous frequency synthesizer' [patent_app_type] => utility [patent_app_number] => 10/760990 [patent_app_country] => US [patent_app_date] => 2004-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2992 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/906/06906560.pdf [firstpage_image] =>[orig_patent_app_number] => 10760990 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/760990
Phase-continuous frequency synthesizer Jan 19, 2004 Issued
Array ( [id] => 7037206 [patent_doc_number] => 20050156640 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-21 [patent_title] => 'Novel charge leakage correction circuit for applications in PLLs' [patent_app_type] => utility [patent_app_number] => 10/759942 [patent_app_country] => US [patent_app_date] => 2004-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2149 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0156/20050156640.pdf [firstpage_image] =>[orig_patent_app_number] => 10759942 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/759942
Charge leakage correction circuit for applications in PLLs Jan 15, 2004 Issued
Array ( [id] => 775111 [patent_doc_number] => 07002385 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-02-21 [patent_title] => 'Circuit arrangement and method for producing a pulse width modulated signal' [patent_app_type] => utility [patent_app_number] => 10/753508 [patent_app_country] => US [patent_app_date] => 2004-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 4274 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/002/07002385.pdf [firstpage_image] =>[orig_patent_app_number] => 10753508 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/753508
Circuit arrangement and method for producing a pulse width modulated signal Jan 7, 2004 Issued
Array ( [id] => 7175894 [patent_doc_number] => 20040201408 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-14 [patent_title] => 'Delay locked loop and a method for delay control' [patent_app_type] => new [patent_app_number] => 10/748711 [patent_app_country] => US [patent_app_date] => 2003-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4070 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 3 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0201/20040201408.pdf [firstpage_image] =>[orig_patent_app_number] => 10748711 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/748711
Delay locked loop and a method for delay control Dec 29, 2003 Abandoned
Array ( [id] => 935824 [patent_doc_number] => 06975174 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-12-13 [patent_title] => 'Clock oscillator' [patent_app_type] => utility [patent_app_number] => 10/749798 [patent_app_country] => US [patent_app_date] => 2003-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2310 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/975/06975174.pdf [firstpage_image] =>[orig_patent_app_number] => 10749798 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/749798
Clock oscillator Dec 29, 2003 Issued
Array ( [id] => 7621960 [patent_doc_number] => 06977541 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-12-20 [patent_title] => 'Variable time constant circuit and filter circuit using the same' [patent_app_type] => utility [patent_app_number] => 10/743949 [patent_app_country] => US [patent_app_date] => 2003-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 5416 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 351 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/977/06977541.pdf [firstpage_image] =>[orig_patent_app_number] => 10743949 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/743949
Variable time constant circuit and filter circuit using the same Dec 23, 2003 Issued
Array ( [id] => 7423443 [patent_doc_number] => 20040183517 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-23 [patent_title] => 'Generation and measurement of timing delays by digital phase error compensation' [patent_app_type] => new [patent_app_number] => 10/744834 [patent_app_country] => US [patent_app_date] => 2003-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 15484 [patent_no_of_claims] => 60 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0183/20040183517.pdf [firstpage_image] =>[orig_patent_app_number] => 10744834 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/744834
Generation and measurement of timing delays by digital phase error compensation Dec 22, 2003 Issued
Array ( [id] => 7364599 [patent_doc_number] => 20040217788 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-04 [patent_title] => 'Digital delay locked loop and control method thereof' [patent_app_type] => new [patent_app_number] => 10/745745 [patent_app_country] => US [patent_app_date] => 2003-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7519 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0217/20040217788.pdf [firstpage_image] =>[orig_patent_app_number] => 10745745 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/745745
Digital delay locked loop and control method thereof Dec 22, 2003 Issued
Array ( [id] => 6994559 [patent_doc_number] => 20050134337 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-23 [patent_title] => 'Clock signal distribution with reduced parasitic loading effects' [patent_app_type] => utility [patent_app_number] => 10/744206 [patent_app_country] => US [patent_app_date] => 2003-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3909 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0134/20050134337.pdf [firstpage_image] =>[orig_patent_app_number] => 10744206 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/744206
Clock signal distribution with reduced parasitic loading effects Dec 21, 2003 Issued
Array ( [id] => 709152 [patent_doc_number] => 07061291 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-13 [patent_title] => 'Linear voltage tracking amplifier for negative supply slew rate control' [patent_app_type] => utility [patent_app_number] => 10/743171 [patent_app_country] => US [patent_app_date] => 2003-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3460 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/061/07061291.pdf [firstpage_image] =>[orig_patent_app_number] => 10743171 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/743171
Linear voltage tracking amplifier for negative supply slew rate control Dec 21, 2003 Issued
Array ( [id] => 7329772 [patent_doc_number] => 20040130364 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-08 [patent_title] => 'Charge pump circuit and PLL circuit using same' [patent_app_type] => new [patent_app_number] => 10/739109 [patent_app_country] => US [patent_app_date] => 2003-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11049 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 259 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0130/20040130364.pdf [firstpage_image] =>[orig_patent_app_number] => 10739109 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/739109
Charge pump circuit and PLL circuit using same Dec 18, 2003 Issued
Array ( [id] => 527792 [patent_doc_number] => 07187220 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-03-06 [patent_title] => 'Memory clock slowdown' [patent_app_type] => utility [patent_app_number] => 10/741149 [patent_app_country] => US [patent_app_date] => 2003-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 6599 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/187/07187220.pdf [firstpage_image] =>[orig_patent_app_number] => 10741149 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/741149
Memory clock slowdown Dec 17, 2003 Issued
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