
An T. Luu
Examiner (ID: 5797, Phone: (571)272-1746 , Office: P/2842 )
| Most Active Art Unit | 2816 |
| Art Unit(s) | 2502, 2816, 2842 |
| Total Applications | 2105 |
| Issued Applications | 1967 |
| Pending Applications | 23 |
| Abandoned Applications | 118 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 730878
[patent_doc_number] => 07042263
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[patent_title] => 'Memory clock slowdown synthesis circuit'
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[patent_app_number] => 10/742572
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/742572 | Memory clock slowdown synthesis circuit | Dec 17, 2003 | Issued |
Array
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[patent_title] => 'Generating multi-phase clock signals using hierarchical delays'
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Array
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[patent_issue_date] => 2006-01-03
[patent_title] => 'Digital frequency-multiplying DLLs'
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[patent_app_date] => 2003-12-11
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Array
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[patent_issue_date] => 2005-09-13
[patent_title] => 'Methods and arrangements for a low power phase-locked loop'
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Array
(
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[patent_title] => 'Quasi-feedforward PWM modulator'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/728592 | Quasi-feedforward PWM modulator | Dec 3, 2003 | Issued |
Array
(
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[patent_title] => 'Temperature adaptive refresh clock generator for refresh operation'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/726320 | Temperature adaptive refresh clock generator for refresh operation | Nov 30, 2003 | Abandoned |
Array
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Array
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[id] => 6937018
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[patent_title] => 'Generating an oscillating signal according to a control current'
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Array
(
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[patent_title] => 'Class AB digital to analog converter/line driver'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/720144 | Class AB digital to analog converter/line driver | Nov 24, 2003 | Issued |
Array
(
[id] => 6936975
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[patent_issue_date] => 2005-05-26
[patent_title] => 'PHASE FREQUENCY DETECTOR WITH PROGRAMMABLE MINIMUM PULSE WIDTH'
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[patent_app_number] => 10/707178
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/707178 | Phase frequency detector with programmable minimum pulse width | Nov 24, 2003 | Issued |
Array
(
[id] => 5818417
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Array
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Array
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Array
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Array
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Array
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Array
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Array
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