Search

An T. Luu

Examiner (ID: 5797, Phone: (571)272-1746 , Office: P/2842 )

Most Active Art Unit
2816
Art Unit(s)
2502, 2816, 2842
Total Applications
2105
Issued Applications
1967
Pending Applications
23
Abandoned Applications
118

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 730878 [patent_doc_number] => 07042263 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-05-09 [patent_title] => 'Memory clock slowdown synthesis circuit' [patent_app_type] => utility [patent_app_number] => 10/742572 [patent_app_country] => US [patent_app_date] => 2003-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 6792 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/042/07042263.pdf [firstpage_image] =>[orig_patent_app_number] => 10742572 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/742572
Memory clock slowdown synthesis circuit Dec 17, 2003 Issued
Array ( [id] => 767562 [patent_doc_number] => 07009434 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-07 [patent_title] => 'Generating multi-phase clock signals using hierarchical delays' [patent_app_type] => utility [patent_app_number] => 10/734506 [patent_app_country] => US [patent_app_date] => 2003-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3677 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/009/07009434.pdf [firstpage_image] =>[orig_patent_app_number] => 10734506 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/734506
Generating multi-phase clock signals using hierarchical delays Dec 11, 2003 Issued
Array ( [id] => 793533 [patent_doc_number] => 06982579 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-03 [patent_title] => 'Digital frequency-multiplying DLLs' [patent_app_type] => utility [patent_app_number] => 10/734339 [patent_app_country] => US [patent_app_date] => 2003-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3949 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/982/06982579.pdf [firstpage_image] =>[orig_patent_app_number] => 10734339 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/734339
Digital frequency-multiplying DLLs Dec 10, 2003 Issued
Array ( [id] => 7619587 [patent_doc_number] => 06943599 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-09-13 [patent_title] => 'Methods and arrangements for a low power phase-locked loop' [patent_app_type] => utility [patent_app_number] => 10/733933 [patent_app_country] => US [patent_app_date] => 2003-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5034 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/943/06943599.pdf [firstpage_image] =>[orig_patent_app_number] => 10733933 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/733933
Methods and arrangements for a low power phase-locked loop Dec 9, 2003 Issued
Array ( [id] => 979520 [patent_doc_number] => 06930526 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-08-16 [patent_title] => 'Quasi-feedforward PWM modulator' [patent_app_type] => utility [patent_app_number] => 10/728592 [patent_app_country] => US [patent_app_date] => 2003-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 2699 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/930/06930526.pdf [firstpage_image] =>[orig_patent_app_number] => 10728592 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/728592
Quasi-feedforward PWM modulator Dec 3, 2003 Issued
Array ( [id] => 7286349 [patent_doc_number] => 20040108521 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-10 [patent_title] => 'Temperature adaptive refresh clock generator for refresh operation' [patent_app_type] => new [patent_app_number] => 10/726320 [patent_app_country] => US [patent_app_date] => 2003-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4153 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0108/20040108521.pdf [firstpage_image] =>[orig_patent_app_number] => 10726320 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/726320
Temperature adaptive refresh clock generator for refresh operation Nov 30, 2003 Abandoned
Array ( [id] => 793532 [patent_doc_number] => 06982578 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-03 [patent_title] => 'Digital delay-locked loop circuits with hierarchical delay adjustment' [patent_app_type] => utility [patent_app_number] => 10/722959 [patent_app_country] => US [patent_app_date] => 2003-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5991 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/982/06982578.pdf [firstpage_image] =>[orig_patent_app_number] => 10722959 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/722959
Digital delay-locked loop circuits with hierarchical delay adjustment Nov 25, 2003 Issued
Array ( [id] => 6937018 [patent_doc_number] => 20050110579 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-26 [patent_title] => 'Generating an oscillating signal according to a control current' [patent_app_type] => utility [patent_app_number] => 10/722930 [patent_app_country] => US [patent_app_date] => 2003-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3685 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0110/20050110579.pdf [firstpage_image] =>[orig_patent_app_number] => 10722930 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/722930
Generating an oscillating signal according to a control current Nov 24, 2003 Issued
Array ( [id] => 1044477 [patent_doc_number] => 06867621 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-03-15 [patent_title] => 'Class AB digital to analog converter/line driver' [patent_app_type] => utility [patent_app_number] => 10/720144 [patent_app_country] => US [patent_app_date] => 2003-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4504 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/867/06867621.pdf [firstpage_image] =>[orig_patent_app_number] => 10720144 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/720144
Class AB digital to analog converter/line driver Nov 24, 2003 Issued
Array ( [id] => 6936975 [patent_doc_number] => 20050110536 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-26 [patent_title] => 'PHASE FREQUENCY DETECTOR WITH PROGRAMMABLE MINIMUM PULSE WIDTH' [patent_app_type] => utility [patent_app_number] => 10/707178 [patent_app_country] => US [patent_app_date] => 2003-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2808 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0110/20050110536.pdf [firstpage_image] =>[orig_patent_app_number] => 10707178 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/707178
Phase frequency detector with programmable minimum pulse width Nov 24, 2003 Issued
Array ( [id] => 5818417 [patent_doc_number] => 20060022730 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-02 [patent_title] => 'Hardware/software implementation of a pwm with enhanced features using a standard microprocessor' [patent_app_type] => utility [patent_app_number] => 10/537577 [patent_app_country] => US [patent_app_date] => 2003-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1873 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0022/20060022730.pdf [firstpage_image] =>[orig_patent_app_number] => 10537577 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/537577
Hardware/software implementation of a PWM with enhanced features using a standard microprocessor Nov 24, 2003 Issued
Array ( [id] => 7101946 [patent_doc_number] => 20050104672 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-19 [patent_title] => 'Method and apparatus to improve frequency stability of an integrated circuit oscillator' [patent_app_type] => utility [patent_app_number] => 10/717228 [patent_app_country] => US [patent_app_date] => 2003-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3698 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0104/20050104672.pdf [firstpage_image] =>[orig_patent_app_number] => 10717228 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/717228
Method and apparatus to improve frequency stability of an integrated circuit oscillator Nov 18, 2003 Issued
Array ( [id] => 7415399 [patent_doc_number] => 20040107060 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-03 [patent_title] => 'Output circuit and method for reducing simultaneous switching output skew' [patent_app_type] => new [patent_app_number] => 10/717111 [patent_app_country] => US [patent_app_date] => 2003-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5922 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0107/20040107060.pdf [firstpage_image] =>[orig_patent_app_number] => 10717111 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/717111
Output circuit and method for reducing simultaneous switching output skew Nov 18, 2003 Issued
Array ( [id] => 857732 [patent_doc_number] => 07375564 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-05-20 [patent_title] => 'Time delay compensation circuit comprising delay cells having various unit time delays' [patent_app_type] => utility [patent_app_number] => 10/716146 [patent_app_country] => US [patent_app_date] => 2003-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 4623 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/375/07375564.pdf [firstpage_image] =>[orig_patent_app_number] => 10716146 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/716146
Time delay compensation circuit comprising delay cells having various unit time delays Nov 17, 2003 Issued
Array ( [id] => 703623 [patent_doc_number] => 07064600 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-06-20 [patent_title] => 'Limit swing charge pump and method thereof' [patent_app_type] => utility [patent_app_number] => 10/703375 [patent_app_country] => US [patent_app_date] => 2003-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 3071 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/064/07064600.pdf [firstpage_image] =>[orig_patent_app_number] => 10703375 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/703375
Limit swing charge pump and method thereof Nov 6, 2003 Issued
Array ( [id] => 700730 [patent_doc_number] => 07068084 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-27 [patent_title] => 'Delay locked loop capable of compensating for delay of internal clock signal by variation of driving strength of output driver in semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 10/702838 [patent_app_country] => US [patent_app_date] => 2003-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1840 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/068/07068084.pdf [firstpage_image] =>[orig_patent_app_number] => 10702838 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/702838
Delay locked loop capable of compensating for delay of internal clock signal by variation of driving strength of output driver in semiconductor memory device Nov 5, 2003 Issued
Array ( [id] => 1081685 [patent_doc_number] => 06836164 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-12-28 [patent_title] => 'Programmable phase shift circuitry' [patent_app_type] => B1 [patent_app_number] => 10/702300 [patent_app_country] => US [patent_app_date] => 2003-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 25 [patent_no_of_words] => 9432 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/836/06836164.pdf [firstpage_image] =>[orig_patent_app_number] => 10702300 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/702300
Programmable phase shift circuitry Nov 4, 2003 Issued
Array ( [id] => 673382 [patent_doc_number] => 07091763 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-08-15 [patent_title] => 'Clock generation' [patent_app_type] => utility [patent_app_number] => 10/701005 [patent_app_country] => US [patent_app_date] => 2003-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 2944 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/091/07091763.pdf [firstpage_image] =>[orig_patent_app_number] => 10701005 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/701005
Clock generation Nov 2, 2003 Issued
Array ( [id] => 954220 [patent_doc_number] => 06958635 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-10-25 [patent_title] => 'Low-power direct digital synthesizer with analog interpolation' [patent_app_type] => utility [patent_app_number] => 10/684797 [patent_app_country] => US [patent_app_date] => 2003-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 8104 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/958/06958635.pdf [firstpage_image] =>[orig_patent_app_number] => 10684797 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/684797
Low-power direct digital synthesizer with analog interpolation Oct 13, 2003 Issued
Array ( [id] => 1028734 [patent_doc_number] => 06882189 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-04-19 [patent_title] => 'Programmable divider with built-in programmable delay chain for high-speed/low power application' [patent_app_type] => utility [patent_app_number] => 10/683262 [patent_app_country] => US [patent_app_date] => 2003-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5159 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/882/06882189.pdf [firstpage_image] =>[orig_patent_app_number] => 10683262 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/683262
Programmable divider with built-in programmable delay chain for high-speed/low power application Oct 13, 2003 Issued
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