
An T. Luu
Examiner (ID: 5797, Phone: (571)272-1746 , Office: P/2842 )
| Most Active Art Unit | 2816 |
| Art Unit(s) | 2502, 2816, 2842 |
| Total Applications | 2105 |
| Issued Applications | 1967 |
| Pending Applications | 23 |
| Abandoned Applications | 118 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7222513
[patent_doc_number] => 20050077932
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-04-14
[patent_title] => 'Synchronizer apparatus for synchronizing data from one clock domain to another clock domain'
[patent_app_type] => utility
[patent_app_number] => 10/684093
[patent_app_country] => US
[patent_app_date] => 2003-10-10
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[pdf_file] => publications/A1/0077/20050077932.pdf
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Array
(
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[patent_doc_number] => 20050077935
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-04-14
[patent_title] => 'SPREAD-SPECTRUM CLOCK GENERATOR USING PROCESSING IN THE BITSTREAM DOMAIN'
[patent_app_type] => utility
[patent_app_number] => 10/682839
[patent_app_country] => US
[patent_app_date] => 2003-10-10
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Array
(
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[patent_doc_number] => 20050001665
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[patent_kind] => A1
[patent_issue_date] => 2005-01-06
[patent_title] => 'Method for multiple-phase splitting by phase interpolation and circuit the same'
[patent_app_type] => utility
[patent_app_number] => 10/680150
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[patent_app_date] => 2003-10-08
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/680150 | Method for multiple-phase splitting by phase interpolation and circuit the same | Oct 7, 2003 | Issued |
Array
(
[id] => 462181
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[patent_kind] => B2
[patent_issue_date] => 2007-07-10
[patent_title] => 'Voltage control for clock generating circuit'
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[patent_app_number] => 10/680498
[patent_app_country] => US
[patent_app_date] => 2003-10-06
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/680498 | Voltage control for clock generating circuit | Oct 5, 2003 | Issued |
Array
(
[id] => 624129
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[patent_issue_date] => 2006-11-21
[patent_title] => 'Single VCO/loop filter to control a wobble and read circuit of a DVD and/or CD recorder'
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[patent_app_number] => 10/674165
[patent_app_country] => US
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Array
(
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[patent_issue_date] => 2004-04-01
[patent_title] => 'Loop filter and method for adjusting a compensating current of the same'
[patent_app_type] => new
[patent_app_number] => 10/668218
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/668218 | Loop filter and method for adjusting a compensating current of the same | Sep 23, 2003 | Issued |
Array
(
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[patent_issue_date] => 2005-03-15
[patent_title] => 'Method and apparatus for high frequency digital carrier synthesis from plural intermediate carrier waveforms'
[patent_app_type] => utility
[patent_app_number] => 10/668193
[patent_app_country] => US
[patent_app_date] => 2003-09-24
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/668193 | Method and apparatus for high frequency digital carrier synthesis from plural intermediate carrier waveforms | Sep 23, 2003 | Issued |
Array
(
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[patent_doc_number] => 20040056695
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[patent_kind] => A1
[patent_issue_date] => 2004-03-25
[patent_title] => 'PLL/DLL circuitry programmable for high bandwidth and low bandwidth applications'
[patent_app_type] => new
[patent_app_number] => 10/669295
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/669295 | PLL/DLL circuitry programmable for high bandwidth and low bandwidth applications | Sep 22, 2003 | Issued |
Array
(
[id] => 973012
[patent_doc_number] => 06937077
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[patent_issue_date] => 2005-08-30
[patent_title] => 'Apparatus and method for suppressing jitter within a clock signal generator'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/668755 | Apparatus and method for suppressing jitter within a clock signal generator | Sep 22, 2003 | Issued |
Array
(
[id] => 779930
[patent_doc_number] => 06995590
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[patent_issue_date] => 2006-02-07
[patent_title] => 'Hybrid phase/delay locked loop circuits and methods'
[patent_app_type] => utility
[patent_app_number] => 10/668447
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/668447 | Hybrid phase/delay locked loop circuits and methods | Sep 21, 2003 | Issued |
Array
(
[id] => 5746113
[patent_doc_number] => 20060109043
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[patent_issue_date] => 2006-05-25
[patent_title] => 'Pulse generator'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/531017 | Pulse generator | Sep 18, 2003 | Abandoned |
Array
(
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Array
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Array
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Array
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Array
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Array
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Array
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Array
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/628384 | Semiconductor circuit device having hierarchical power supply structure | Jul 28, 2003 | Issued |