Search

An T. Luu

Examiner (ID: 5797, Phone: (571)272-1746 , Office: P/2842 )

Most Active Art Unit
2816
Art Unit(s)
2502, 2816, 2842
Total Applications
2105
Issued Applications
1967
Pending Applications
23
Abandoned Applications
118

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7222513 [patent_doc_number] => 20050077932 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-14 [patent_title] => 'Synchronizer apparatus for synchronizing data from one clock domain to another clock domain' [patent_app_type] => utility [patent_app_number] => 10/684093 [patent_app_country] => US [patent_app_date] => 2003-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2541 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0077/20050077932.pdf [firstpage_image] =>[orig_patent_app_number] => 10684093 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/684093
Synchronizer apparatus for synchronizing data from one clock domain to another clock domain Oct 9, 2003 Issued
Array ( [id] => 7222542 [patent_doc_number] => 20050077935 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-14 [patent_title] => 'SPREAD-SPECTRUM CLOCK GENERATOR USING PROCESSING IN THE BITSTREAM DOMAIN' [patent_app_type] => utility [patent_app_number] => 10/682839 [patent_app_country] => US [patent_app_date] => 2003-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3407 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0077/20050077935.pdf [firstpage_image] =>[orig_patent_app_number] => 10682839 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/682839
Spread-spectrum clock generator using processing in the bitstream domain Oct 9, 2003 Issued
Array ( [id] => 7059306 [patent_doc_number] => 20050001665 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-06 [patent_title] => 'Method for multiple-phase splitting by phase interpolation and circuit the same' [patent_app_type] => utility [patent_app_number] => 10/680150 [patent_app_country] => US [patent_app_date] => 2003-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 10785 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20050001665.pdf [firstpage_image] =>[orig_patent_app_number] => 10680150 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/680150
Method for multiple-phase splitting by phase interpolation and circuit the same Oct 7, 2003 Issued
Array ( [id] => 462181 [patent_doc_number] => 07242261 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-10 [patent_title] => 'Voltage control for clock generating circuit' [patent_app_type] => utility [patent_app_number] => 10/680498 [patent_app_country] => US [patent_app_date] => 2003-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 6200 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/242/07242261.pdf [firstpage_image] =>[orig_patent_app_number] => 10680498 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/680498
Voltage control for clock generating circuit Oct 5, 2003 Issued
Array ( [id] => 624129 [patent_doc_number] => 07138840 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-11-21 [patent_title] => 'Single VCO/loop filter to control a wobble and read circuit of a DVD and/or CD recorder' [patent_app_type] => utility [patent_app_number] => 10/674165 [patent_app_country] => US [patent_app_date] => 2003-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 4958 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/138/07138840.pdf [firstpage_image] =>[orig_patent_app_number] => 10674165 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/674165
Single VCO/loop filter to control a wobble and read circuit of a DVD and/or CD recorder Sep 28, 2003 Issued
Array ( [id] => 7279174 [patent_doc_number] => 20040061551 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-01 [patent_title] => 'Loop filter and method for adjusting a compensating current of the same' [patent_app_type] => new [patent_app_number] => 10/668218 [patent_app_country] => US [patent_app_date] => 2003-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3620 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20040061551.pdf [firstpage_image] =>[orig_patent_app_number] => 10668218 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/668218
Loop filter and method for adjusting a compensating current of the same Sep 23, 2003 Issued
Array ( [id] => 1044486 [patent_doc_number] => 06867625 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-03-15 [patent_title] => 'Method and apparatus for high frequency digital carrier synthesis from plural intermediate carrier waveforms' [patent_app_type] => utility [patent_app_number] => 10/668193 [patent_app_country] => US [patent_app_date] => 2003-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6206 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/867/06867625.pdf [firstpage_image] =>[orig_patent_app_number] => 10668193 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/668193
Method and apparatus for high frequency digital carrier synthesis from plural intermediate carrier waveforms Sep 23, 2003 Issued
Array ( [id] => 7268177 [patent_doc_number] => 20040056695 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-25 [patent_title] => 'PLL/DLL circuitry programmable for high bandwidth and low bandwidth applications' [patent_app_type] => new [patent_app_number] => 10/669295 [patent_app_country] => US [patent_app_date] => 2003-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8271 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 267 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0056/20040056695.pdf [firstpage_image] =>[orig_patent_app_number] => 10669295 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/669295
PLL/DLL circuitry programmable for high bandwidth and low bandwidth applications Sep 22, 2003 Issued
Array ( [id] => 973012 [patent_doc_number] => 06937077 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-30 [patent_title] => 'Apparatus and method for suppressing jitter within a clock signal generator' [patent_app_type] => utility [patent_app_number] => 10/668755 [patent_app_country] => US [patent_app_date] => 2003-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 9560 [patent_no_of_claims] => 69 [patent_no_of_ind_claims] => 24 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/937/06937077.pdf [firstpage_image] =>[orig_patent_app_number] => 10668755 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/668755
Apparatus and method for suppressing jitter within a clock signal generator Sep 22, 2003 Issued
Array ( [id] => 779930 [patent_doc_number] => 06995590 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-02-07 [patent_title] => 'Hybrid phase/delay locked loop circuits and methods' [patent_app_type] => utility [patent_app_number] => 10/668447 [patent_app_country] => US [patent_app_date] => 2003-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 4436 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/995/06995590.pdf [firstpage_image] =>[orig_patent_app_number] => 10668447 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/668447
Hybrid phase/delay locked loop circuits and methods Sep 21, 2003 Issued
Array ( [id] => 5746113 [patent_doc_number] => 20060109043 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-25 [patent_title] => 'Pulse generator' [patent_app_type] => utility [patent_app_number] => 10/531017 [patent_app_country] => US [patent_app_date] => 2003-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2232 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20060109043.pdf [firstpage_image] =>[orig_patent_app_number] => 10531017 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/531017
Pulse generator Sep 18, 2003 Abandoned
Array ( [id] => 7023386 [patent_doc_number] => 20050017780 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-27 [patent_title] => 'Digital control variable delay circuit which is hardly susceptible to noise' [patent_app_type] => utility [patent_app_number] => 10/659364 [patent_app_country] => US [patent_app_date] => 2003-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3903 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0017/20050017780.pdf [firstpage_image] =>[orig_patent_app_number] => 10659364 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/659364
Digital control variable delay circuit which is hardly susceptible to noise Sep 10, 2003 Issued
Array ( [id] => 1006410 [patent_doc_number] => 06906569 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-06-14 [patent_title] => 'Digital signal delay device' [patent_app_type] => utility [patent_app_number] => 10/658742 [patent_app_country] => US [patent_app_date] => 2003-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 6383 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/906/06906569.pdf [firstpage_image] =>[orig_patent_app_number] => 10658742 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/658742
Digital signal delay device Sep 9, 2003 Issued
Array ( [id] => 415761 [patent_doc_number] => 07279947 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-09 [patent_title] => 'PWM buffer circuit for adjusting a frequency and a duty cycle of a PWM signal' [patent_app_type] => utility [patent_app_number] => 10/657181 [patent_app_country] => US [patent_app_date] => 2003-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 2752 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/279/07279947.pdf [firstpage_image] =>[orig_patent_app_number] => 10657181 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/657181
PWM buffer circuit for adjusting a frequency and a duty cycle of a PWM signal Sep 8, 2003 Issued
Array ( [id] => 985976 [patent_doc_number] => 06924710 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-02 [patent_title] => 'Voltage ID based frequency control for clock generating circuit' [patent_app_type] => utility [patent_app_number] => 10/659637 [patent_app_country] => US [patent_app_date] => 2003-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 7449 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/924/06924710.pdf [firstpage_image] =>[orig_patent_app_number] => 10659637 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/659637
Voltage ID based frequency control for clock generating circuit Sep 8, 2003 Issued
Array ( [id] => 7612235 [patent_doc_number] => 06903602 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-06-07 [patent_title] => 'Calibrated fully differential RC filter' [patent_app_type] => utility [patent_app_number] => 10/657618 [patent_app_country] => US [patent_app_date] => 2003-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3611 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/903/06903602.pdf [firstpage_image] =>[orig_patent_app_number] => 10657618 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/657618
Calibrated fully differential RC filter Sep 7, 2003 Issued
Array ( [id] => 991222 [patent_doc_number] => 06919749 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-07-19 [patent_title] => 'Apparatus and method for a digital delay locked loop' [patent_app_type] => utility [patent_app_number] => 10/658710 [patent_app_country] => US [patent_app_date] => 2003-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 8292 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/919/06919749.pdf [firstpage_image] =>[orig_patent_app_number] => 10658710 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/658710
Apparatus and method for a digital delay locked loop Sep 7, 2003 Issued
Array ( [id] => 756983 [patent_doc_number] => 07019570 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-28 [patent_title] => 'Dual-gain loop circuitry for programmable logic device' [patent_app_type] => utility [patent_app_number] => 10/655853 [patent_app_country] => US [patent_app_date] => 2003-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 6468 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 291 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/019/07019570.pdf [firstpage_image] =>[orig_patent_app_number] => 10655853 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/655853
Dual-gain loop circuitry for programmable logic device Sep 4, 2003 Issued
Array ( [id] => 783727 [patent_doc_number] => 06992515 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-01-31 [patent_title] => 'Clock signal duty cycle adjust circuit' [patent_app_type] => utility [patent_app_number] => 10/643576 [patent_app_country] => US [patent_app_date] => 2003-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5398 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/992/06992515.pdf [firstpage_image] =>[orig_patent_app_number] => 10643576 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/643576
Clock signal duty cycle adjust circuit Aug 17, 2003 Issued
Array ( [id] => 444139 [patent_doc_number] => 07256644 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-08-14 [patent_title] => 'Semiconductor circuit device having hierarchical power supply structure' [patent_app_type] => utility [patent_app_number] => 10/628384 [patent_app_country] => US [patent_app_date] => 2003-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 24 [patent_no_of_words] => 15255 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/256/07256644.pdf [firstpage_image] =>[orig_patent_app_number] => 10628384 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/628384
Semiconductor circuit device having hierarchical power supply structure Jul 28, 2003 Issued
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