Search

An T. Luu

Examiner (ID: 5797, Phone: (571)272-1746 , Office: P/2842 )

Most Active Art Unit
2816
Art Unit(s)
2502, 2816, 2842
Total Applications
2105
Issued Applications
1967
Pending Applications
23
Abandoned Applications
118

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6849713 [patent_doc_number] => 20030141915 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-31 [patent_title] => 'Delay control circuit device, and a semiconductor integrated circuit device and a delay control method using said delay control circuit device' [patent_app_type] => new [patent_app_number] => 10/339322 [patent_app_country] => US [patent_app_date] => 2003-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5624 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0141/20030141915.pdf [firstpage_image] =>[orig_patent_app_number] => 10339322 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/339322
Delay control circuit device, and a semiconductor integrated circuit device and a delay control method using said delay control circuit device Jan 9, 2003 Issued
Array ( [id] => 7319418 [patent_doc_number] => 20040135607 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-15 [patent_title] => 'Clock frequency multiplier' [patent_app_type] => new [patent_app_number] => 10/339214 [patent_app_country] => US [patent_app_date] => 2003-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3204 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0135/20040135607.pdf [firstpage_image] =>[orig_patent_app_number] => 10339214 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/339214
Clock frequency multiplier Jan 8, 2003 Issued
Array ( [id] => 7328611 [patent_doc_number] => 20040139261 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-15 [patent_title] => 'Method and apparatus for supplying a reference voltage for chip-to-chip communication' [patent_app_type] => new [patent_app_number] => 10/339754 [patent_app_country] => US [patent_app_date] => 2003-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3459 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0139/20040139261.pdf [firstpage_image] =>[orig_patent_app_number] => 10339754 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/339754
Method and apparatus for supplying a reference voltage for chip-to-chip communication Jan 8, 2003 Issued
Array ( [id] => 7329791 [patent_doc_number] => 20040130373 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-08 [patent_title] => 'Low-swing impedance controlled unity gain differential clock driver' [patent_app_type] => new [patent_app_number] => 10/338229 [patent_app_country] => US [patent_app_date] => 2003-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2309 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0130/20040130373.pdf [firstpage_image] =>[orig_patent_app_number] => 10338229 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/338229
Low-swing impedance controlled unity gain differential clock driver Jan 7, 2003 Abandoned
Array ( [id] => 1133514 [patent_doc_number] => 06788123 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-07 [patent_title] => 'Unity gain interpolator for delay locked loops' [patent_app_type] => B2 [patent_app_number] => 10/338224 [patent_app_country] => US [patent_app_date] => 2003-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3353 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/788/06788123.pdf [firstpage_image] =>[orig_patent_app_number] => 10338224 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/338224
Unity gain interpolator for delay locked loops Jan 7, 2003 Issued
Array ( [id] => 7329774 [patent_doc_number] => 20040130366 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-08 [patent_title] => 'METHOD AND SYSTEM FOR DELAY CONTROL IN SYNCHRONIZATION CIRCUITS' [patent_app_type] => new [patent_app_number] => 10/339752 [patent_app_country] => US [patent_app_date] => 2003-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7714 [patent_no_of_claims] => 54 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0130/20040130366.pdf [firstpage_image] =>[orig_patent_app_number] => 10339752 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/339752
Method and system for delay control in synchronization circuits Jan 7, 2003 Issued
Array ( [id] => 6695224 [patent_doc_number] => 20030107418 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-12 [patent_title] => 'Dual loop phase lock loops using dual voltage supply regulators' [patent_app_type] => new [patent_app_number] => 10/336570 [patent_app_country] => US [patent_app_date] => 2003-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3215 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0107/20030107418.pdf [firstpage_image] =>[orig_patent_app_number] => 10336570 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/336570
Dual loop phase lock loops using dual voltage supply regulators Jan 2, 2003 Issued
Array ( [id] => 6859298 [patent_doc_number] => 20030090306 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-15 [patent_title] => 'Thermal noise random pulse generator and random number generator' [patent_app_type] => new [patent_app_number] => 10/336465 [patent_app_country] => US [patent_app_date] => 2003-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4543 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0090/20030090306.pdf [firstpage_image] =>[orig_patent_app_number] => 10336465 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/336465
Thermal noise random pulse generator and random number generator Jan 1, 2003 Abandoned
Array ( [id] => 6786094 [patent_doc_number] => 20030137333 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-24 [patent_title] => 'Multiphase-clock processing circuit and clock multiplying circuit' [patent_app_type] => new [patent_app_number] => 10/330017 [patent_app_country] => US [patent_app_date] => 2002-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7972 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0137/20030137333.pdf [firstpage_image] =>[orig_patent_app_number] => 10330017 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/330017
Multiphase-clock processing circuit and clock multiplying circuit Dec 25, 2002 Issued
Array ( [id] => 1237663 [patent_doc_number] => 06690228 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-02-10 [patent_title] => 'Bandgap voltage reference insensitive to voltage offset' [patent_app_type] => B1 [patent_app_number] => 10/316340 [patent_app_country] => US [patent_app_date] => 2002-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3060 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/690/06690228.pdf [firstpage_image] =>[orig_patent_app_number] => 10316340 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/316340
Bandgap voltage reference insensitive to voltage offset Dec 10, 2002 Issued
Array ( [id] => 6854564 [patent_doc_number] => 20030128065 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-10 [patent_title] => 'Circuit assembly for converting a differential input clock signal pair into a single-ended output clock signal' [patent_app_type] => new [patent_app_number] => 10/316337 [patent_app_country] => US [patent_app_date] => 2002-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2856 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0128/20030128065.pdf [firstpage_image] =>[orig_patent_app_number] => 10316337 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/316337
Circuit assembly for converting a differential input clock signal pair into a single-ended output clock signal Dec 10, 2002 Issued
Array ( [id] => 7252241 [patent_doc_number] => 20040239396 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-02 [patent_title] => 'Digital delay line' [patent_app_type] => new [patent_app_number] => 10/485599 [patent_app_country] => US [patent_app_date] => 2004-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3275 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 3 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0239/20040239396.pdf [firstpage_image] =>[orig_patent_app_number] => 10485599 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/485599
Digital delay line Dec 10, 2002 Issued
Array ( [id] => 1267070 [patent_doc_number] => 06661261 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-12-09 [patent_title] => 'Programmable divider with built-in programmable delay chain for high-speed/low power application' [patent_app_type] => B2 [patent_app_number] => 10/314954 [patent_app_country] => US [patent_app_date] => 2002-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5133 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/661/06661261.pdf [firstpage_image] =>[orig_patent_app_number] => 10314954 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/314954
Programmable divider with built-in programmable delay chain for high-speed/low power application Dec 9, 2002 Issued
Array ( [id] => 1230435 [patent_doc_number] => 06696884 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-02-24 [patent_title] => 'Method and apparatus to achieve long time constants with a small MOS gate capacitor' [patent_app_type] => B1 [patent_app_number] => 10/316302 [patent_app_country] => US [patent_app_date] => 2002-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6658 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/696/06696884.pdf [firstpage_image] =>[orig_patent_app_number] => 10316302 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/316302
Method and apparatus to achieve long time constants with a small MOS gate capacitor Dec 9, 2002 Issued
Array ( [id] => 1086842 [patent_doc_number] => 06831498 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-12-14 [patent_title] => 'High speed integrated circuit current switch' [patent_app_type] => B2 [patent_app_number] => 10/314472 [patent_app_country] => US [patent_app_date] => 2002-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 1996 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 381 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/831/06831498.pdf [firstpage_image] =>[orig_patent_app_number] => 10314472 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/314472
High speed integrated circuit current switch Dec 8, 2002 Issued
Array ( [id] => 6764340 [patent_doc_number] => 20030098738 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-29 [patent_title] => 'Current generator circuit for high-voltage applications' [patent_app_type] => new [patent_app_number] => 10/303020 [patent_app_country] => US [patent_app_date] => 2002-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2626 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0098/20030098738.pdf [firstpage_image] =>[orig_patent_app_number] => 10303020 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/303020
Current generator circuit for high-voltage applications Nov 24, 2002 Abandoned
Array ( [id] => 6681260 [patent_doc_number] => 20030117124 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-26 [patent_title] => 'Digital clock detection' [patent_app_type] => new [patent_app_number] => 10/286276 [patent_app_country] => US [patent_app_date] => 2002-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1258 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0117/20030117124.pdf [firstpage_image] =>[orig_patent_app_number] => 10286276 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/286276
Digital clock detection Oct 31, 2002 Abandoned
Array ( [id] => 7349862 [patent_doc_number] => 20040012425 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-22 [patent_title] => 'Charge-pump phase-locked loop circuit with charge calibration' [patent_app_type] => new [patent_app_number] => 10/279972 [patent_app_country] => US [patent_app_date] => 2002-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3927 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0012/20040012425.pdf [firstpage_image] =>[orig_patent_app_number] => 10279972 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/279972
Charge-pump phase-locked loop circuit with charge calibration Oct 24, 2002 Issued
Array ( [id] => 7629193 [patent_doc_number] => 06819164 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-16 [patent_title] => 'Apparatus and method for a precision bi-directional trim scheme' [patent_app_type] => B1 [patent_app_number] => 10/274313 [patent_app_country] => US [patent_app_date] => 2002-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3981 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 4 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/819/06819164.pdf [firstpage_image] =>[orig_patent_app_number] => 10274313 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/274313
Apparatus and method for a precision bi-directional trim scheme Oct 16, 2002 Issued
Array ( [id] => 7624935 [patent_doc_number] => 06724236 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-20 [patent_title] => 'Buffered bootstrapped input switch with cancelled charge sharing for use in high performance sample and hold switched capacitor circuits' [patent_app_type] => B1 [patent_app_number] => 10/269814 [patent_app_country] => US [patent_app_date] => 2002-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 1608 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/724/06724236.pdf [firstpage_image] =>[orig_patent_app_number] => 10269814 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/269814
Buffered bootstrapped input switch with cancelled charge sharing for use in high performance sample and hold switched capacitor circuits Oct 11, 2002 Issued
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