Ana J. Picon-feliciano

Array ( [id] => 18681076 [patent_doc_number] => 20230318741 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => CONTROL OF ERROR CORRECTION DECODER OPERATION AND USAGE IN A RECEIVER DEVICE [patent_app_type] => utility [patent_app_number] => 17/657115 [patent_app_country] => US [patent_app_date] => 2022-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21829 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17657115 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19944205 [patent_doc_number] => 12316348 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-27 [patent_title] => Polar code segment encoding method and related apparatus [patent_app_type] => utility [patent_app_number] => 18/552626 [patent_app_country] => US [patent_app_date] => 2022-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 13992 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 281 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18552626 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18662097 [patent_doc_number] => 20230308114 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-28 [patent_title] => BIT FLIPPING DECODER WITH DYNAMIC BIT FLIPPING CRITERIA [patent_app_type] => utility [patent_app_number] => 17/706471 [patent_app_country] => US [patent_app_date] => 2022-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8693 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17706471 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18661064 [patent_doc_number] => 20230307077 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-28 [patent_title] => APPARATUS AND METHOD FOR DETECTING ERRORS IN A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/704289 [patent_app_country] => US [patent_app_date] => 2022-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12058 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17704289 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19093695 [patent_doc_number] => 11955159 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-09 [patent_title] => Semiconductor memory device and memory system including the same [patent_app_type] => utility [patent_app_number] => 17/703049 [patent_app_country] => US [patent_app_date] => 2022-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 14064 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 259 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17703049 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18944417 [patent_doc_number] => 20240039556 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-01 [patent_title] => Data Coding Processing Method and Apparatus, Storage Medium, and Electronic Device [patent_app_type] => utility [patent_app_number] => 18/283860 [patent_app_country] => US [patent_app_date] => 2022-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8247 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18283860 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18653210 [patent_doc_number] => 20230299050 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-21 [patent_title] => TEST ARCHITECTURE FOR 3D STACKED CIRCUITS [patent_app_type] => utility [patent_app_number] => 17/700329 [patent_app_country] => US [patent_app_date] => 2022-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11650 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17700329 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20346495 [patent_doc_number] => 12470231 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-11 [patent_title] => Method and apparatus to perform cyclic redundancy check training in a memory module [patent_app_type] => utility [patent_app_number] => 17/688125 [patent_app_country] => US [patent_app_date] => 2022-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2353 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17688125 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18614340 [patent_doc_number] => 20230281077 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-07 [patent_title] => COMPUTATION AND PLACEMENT OF ERROR CORRECTING CODES (ECC) IN A COMPUTING SYSTEM DATA CACHE [patent_app_type] => utility [patent_app_number] => 17/653825 [patent_app_country] => US [patent_app_date] => 2022-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9179 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17653825 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18688918 [patent_doc_number] => 11784668 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-10 [patent_title] => Decoding fec codewords using ldpc codes define by a parity check matrix which is defined by rpc and qc constraints [patent_app_type] => utility [patent_app_number] => 17/666066 [patent_app_country] => US [patent_app_date] => 2022-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 22 [patent_no_of_words] => 9998 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 321 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17666066 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18797485 [patent_doc_number] => 11831331 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-28 [patent_title] => Transmitter and segmentation method thereof [patent_app_type] => utility [patent_app_number] => 17/583458 [patent_app_country] => US [patent_app_date] => 2022-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 30682 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17583458 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18670610 [patent_doc_number] => 11777528 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-03 [patent_title] => System and method for processing control information [patent_app_type] => utility [patent_app_number] => 17/584244 [patent_app_country] => US [patent_app_date] => 2022-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 13365 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17584244 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18209033 [patent_doc_number] => 20230055293 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-23 [patent_title] => POST ERROR CORRECTION CODE REGISTERS FOR CACHE METADATA [patent_app_type] => utility [patent_app_number] => 17/648404 [patent_app_country] => US [patent_app_date] => 2022-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17798 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17648404 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18804147 [patent_doc_number] => 11837310 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-05 [patent_title] => Memory device for correcting pulse duty and memory system including the same [patent_app_type] => utility [patent_app_number] => 17/569144 [patent_app_country] => US [patent_app_date] => 2022-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 13329 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17569144 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19405702 [patent_doc_number] => 20240289213 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-29 [patent_title] => SYSTEM, METHOD AND APPARATUS FOR REDUCING POWER CONSUMPTION OF ERROR CORRECTION CODING USING COMPACTED DATA BLOCKS [patent_app_type] => utility [patent_app_number] => 18/572226 [patent_app_country] => US [patent_app_date] => 2022-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9598 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18572226 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19405702 [patent_doc_number] => 20240289213 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-29 [patent_title] => SYSTEM, METHOD AND APPARATUS FOR REDUCING POWER CONSUMPTION OF ERROR CORRECTION CODING USING COMPACTED DATA BLOCKS [patent_app_type] => utility [patent_app_number] => 18/572226 [patent_app_country] => US [patent_app_date] => 2022-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9598 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18572226 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18527140 [patent_doc_number] => 11714130 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-01 [patent_title] => Error rate measuring apparatus and error distribution display method [patent_app_type] => utility [patent_app_number] => 17/552608 [patent_app_country] => US [patent_app_date] => 2021-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 8124 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17552608 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18858171 [patent_doc_number] => 11855772 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-26 [patent_title] => High throughput polar ECC decoding via compressed successive cancellation algorithm [patent_app_type] => utility [patent_app_number] => 17/551780 [patent_app_country] => US [patent_app_date] => 2021-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 10071 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17551780 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18670611 [patent_doc_number] => 11777529 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-03 [patent_title] => Binned feedback from receiving device to network encoder [patent_app_type] => utility [patent_app_number] => 17/644243 [patent_app_country] => US [patent_app_date] => 2021-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 14928 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17644243 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18438844 [patent_doc_number] => 20230186139 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-15 [patent_title] => APPARATUS AND METHOD FOR ERROR REDUCTION IN DISTRIBUTED QUANTUM SYSTEMS VIA FUSING-AND-DECOMPOSING GATES [patent_app_type] => utility [patent_app_number] => 17/546974 [patent_app_country] => US [patent_app_date] => 2021-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11319 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17546974 [rel_patent_id] =>[rel_patent_doc_number] =>)