Search

Ana J. Picon-feliciano

Examiner (ID: 3342, Phone: (571)272-5252 , Office: P/2482 )

Most Active Art Unit
2482
Art Unit(s)
2482
Total Applications
463
Issued Applications
290
Pending Applications
56
Abandoned Applications
137

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17956892 [patent_doc_number] => 11483011 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-25 [patent_title] => Decoding method, decoding device, and decoder [patent_app_type] => utility [patent_app_number] => 17/296122 [patent_app_country] => US [patent_app_date] => 2019-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 6371 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17296122 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/296122
Decoding method, decoding device, and decoder Nov 12, 2019 Issued
Array ( [id] => 15622745 [patent_doc_number] => 20200081777 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-12 [patent_title] => DRAM-BASED STORAGE DEVICE AND ASSOCIATED DATA PROCESSING METHOD [patent_app_type] => utility [patent_app_number] => 16/682330 [patent_app_country] => US [patent_app_date] => 2019-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4255 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16682330 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/682330
DRAM-based storage device and associated data processing method Nov 12, 2019 Issued
Array ( [id] => 17048729 [patent_doc_number] => 11101927 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-24 [patent_title] => Data transmission method, base station, and terminal device [patent_app_type] => utility [patent_app_number] => 16/673613 [patent_app_country] => US [patent_app_date] => 2019-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 7814 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16673613 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/673613
Data transmission method, base station, and terminal device Nov 3, 2019 Issued
Array ( [id] => 16810471 [patent_doc_number] => 20210133026 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-06 [patent_title] => Erasure Coded Data Shards Containing Multiple Data Objects [patent_app_type] => utility [patent_app_number] => 16/669853 [patent_app_country] => US [patent_app_date] => 2019-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14535 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16669853 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/669853
Erasure coded data shards containing multiple data objects Oct 30, 2019 Issued
Array ( [id] => 16810469 [patent_doc_number] => 20210133024 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-06 [patent_title] => SYSTEM AND METHOD FOR FACILITATING HIGH-CAPACITY SYSTEM MEMORY ADAPTIVE TO HIGH-ERROR-RATE AND LOW-ENDURANCE MEDIA [patent_app_type] => utility [patent_app_number] => 16/670680 [patent_app_country] => US [patent_app_date] => 2019-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8622 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16670680 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/670680
System and method for facilitating high-capacity system memory adaptive to high-error-rate and low-endurance media Oct 30, 2019 Issued
Array ( [id] => 17017078 [patent_doc_number] => 11086717 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-10 [patent_title] => Random selection of code words for read voltage calibration [patent_app_type] => utility [patent_app_number] => 16/670329 [patent_app_country] => US [patent_app_date] => 2019-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 18 [patent_no_of_words] => 6420 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16670329 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/670329
Random selection of code words for read voltage calibration Oct 30, 2019 Issued
Array ( [id] => 17016332 [patent_doc_number] => 11085965 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-10 [patent_title] => Clock gating and scan clock generation for circuit test [patent_app_type] => utility [patent_app_number] => 16/670146 [patent_app_country] => US [patent_app_date] => 2019-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4827 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16670146 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/670146
Clock gating and scan clock generation for circuit test Oct 30, 2019 Issued
Array ( [id] => 16333190 [patent_doc_number] => 20200304156 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-24 [patent_title] => APPARATUS AND METHOD FOR MANAGING PARITY CHECK MATRIX [patent_app_type] => utility [patent_app_number] => 16/667314 [patent_app_country] => US [patent_app_date] => 2019-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9199 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16667314 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/667314
Apparatus and method for managing parity check matrix Oct 28, 2019 Issued
Array ( [id] => 15836961 [patent_doc_number] => 20200133763 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-30 [patent_title] => PROCESSING OF DATA [patent_app_type] => utility [patent_app_number] => 16/663839 [patent_app_country] => US [patent_app_date] => 2019-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6346 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16663839 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/663839
Processing of data Oct 24, 2019 Issued
Array ( [id] => 17175047 [patent_doc_number] => 20210328718 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-21 [patent_title] => EQUIVALENT PUNCTURE SETS FOR POLAR CODED RE-TRANSMISSIONS [patent_app_type] => utility [patent_app_number] => 17/271746 [patent_app_country] => US [patent_app_date] => 2019-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 31155 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17271746 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/271746
Equivalent puncture sets for polar coded re-transmissions Oct 2, 2019 Issued
Array ( [id] => 17002380 [patent_doc_number] => 11081202 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-03 [patent_title] => Failing address registers for built-in self tests [patent_app_type] => utility [patent_app_number] => 16/589485 [patent_app_country] => US [patent_app_date] => 2019-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6466 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16589485 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/589485
Failing address registers for built-in self tests Sep 30, 2019 Issued
Array ( [id] => 16299814 [patent_doc_number] => 20200285537 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-10 [patent_title] => SEMICONDUCTOR CHIPS [patent_app_type] => utility [patent_app_number] => 16/584569 [patent_app_country] => US [patent_app_date] => 2019-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6615 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16584569 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/584569
SEMICONDUCTOR CHIPS Sep 25, 2019 Abandoned
Array ( [id] => 16732041 [patent_doc_number] => 20210099189 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-01 [patent_title] => CORRECTION DEVICE [patent_app_type] => utility [patent_app_number] => 16/583284 [patent_app_country] => US [patent_app_date] => 2019-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6454 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16583284 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/583284
Correction device Sep 25, 2019 Issued
Array ( [id] => 17046752 [patent_doc_number] => 11099932 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-24 [patent_title] => Controller and memory system [patent_app_type] => utility [patent_app_number] => 16/555264 [patent_app_country] => US [patent_app_date] => 2019-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 6208 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16555264 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/555264
Controller and memory system Aug 28, 2019 Issued
Array ( [id] => 16744453 [patent_doc_number] => 10969433 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-04-06 [patent_title] => Method to compress responses of automatic test pattern generation (ATPG) vectors into an on-chip multiple-input shift register (MISR) [patent_app_type] => utility [patent_app_number] => 16/554059 [patent_app_country] => US [patent_app_date] => 2019-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8419 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16554059 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/554059
Method to compress responses of automatic test pattern generation (ATPG) vectors into an on-chip multiple-input shift register (MISR) Aug 27, 2019 Issued
Array ( [id] => 17209506 [patent_doc_number] => 11169879 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-09 [patent_title] => Storage system [patent_app_type] => utility [patent_app_number] => 16/553360 [patent_app_country] => US [patent_app_date] => 2019-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 17166 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16553360 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/553360
Storage system Aug 27, 2019 Issued
Array ( [id] => 15124989 [patent_doc_number] => 20190349128 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-14 [patent_title] => DATA TRANSMISSION METHOD AND APPARATUS [patent_app_type] => utility [patent_app_number] => 16/522386 [patent_app_country] => US [patent_app_date] => 2019-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12347 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16522386 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/522386
Data transmission method and apparatus Jul 24, 2019 Issued
Array ( [id] => 17180119 [patent_doc_number] => 11157362 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-26 [patent_title] => Elastic storage in a dispersed storage network [patent_app_type] => utility [patent_app_number] => 16/515435 [patent_app_country] => US [patent_app_date] => 2019-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 7258 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16515435 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/515435
Elastic storage in a dispersed storage network Jul 17, 2019 Issued
Array ( [id] => 16910272 [patent_doc_number] => 11042310 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-22 [patent_title] => Reading of start-up information from different memory regions of a memory system [patent_app_type] => utility [patent_app_number] => 16/506475 [patent_app_country] => US [patent_app_date] => 2019-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 23 [patent_no_of_words] => 5288 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16506475 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/506475
Reading of start-up information from different memory regions of a memory system Jul 8, 2019 Issued
Array ( [id] => 17439668 [patent_doc_number] => 11265013 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-01 [patent_title] => Transmitter and segmentation method thereof [patent_app_type] => utility [patent_app_number] => 16/504055 [patent_app_country] => US [patent_app_date] => 2019-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 30898 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 284 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16504055 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/504055
Transmitter and segmentation method thereof Jul 4, 2019 Issued
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