
Ana J. Picon-feliciano
Examiner (ID: 3342, Phone: (571)272-5252 , Office: P/2482 )
| Most Active Art Unit | 2482 |
| Art Unit(s) | 2482 |
| Total Applications | 463 |
| Issued Applications | 290 |
| Pending Applications | 56 |
| Abandoned Applications | 137 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 19891961
[patent_doc_number] => 20250117273
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-04-10
[patent_title] => INDICATING DATA CORRUPTION
[patent_app_type] => utility
[patent_app_number] => 18/774452
[patent_app_country] => US
[patent_app_date] => 2024-07-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8865
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -22
[patent_words_short_claim] => 123
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18774452
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/774452 | INDICATING DATA CORRUPTION | Jul 15, 2024 | Pending |
Array
(
[id] => 19618933
[patent_doc_number] => 20240404613
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-12-05
[patent_title] => RANDOM ACCESS MEMORY AND CORRESPONDING METHOD FOR MANAGING A RANDOM ACCESS MEMORY
[patent_app_type] => utility
[patent_app_number] => 18/773006
[patent_app_country] => US
[patent_app_date] => 2024-07-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 15562
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 153
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18773006
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/773006 | RANDOM ACCESS MEMORY AND CORRESPONDING METHOD FOR MANAGING A RANDOM ACCESS MEMORY | Jul 14, 2024 | Pending |
Array
(
[id] => 19726922
[patent_doc_number] => 20250029673
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-01-23
[patent_title] => BIT INVERSION TECHNIQUES FOR MEMORY SYSTEM REPAIR INDICATIONS
[patent_app_type] => utility
[patent_app_number] => 18/765074
[patent_app_country] => US
[patent_app_date] => 2024-07-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14975
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 170
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18765074
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/765074 | BIT INVERSION TECHNIQUES FOR MEMORY SYSTEM REPAIR INDICATIONS | Jul 4, 2024 | Pending |
Array
(
[id] => 19726922
[patent_doc_number] => 20250029673
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-01-23
[patent_title] => BIT INVERSION TECHNIQUES FOR MEMORY SYSTEM REPAIR INDICATIONS
[patent_app_type] => utility
[patent_app_number] => 18/765074
[patent_app_country] => US
[patent_app_date] => 2024-07-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14975
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 170
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18765074
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/765074 | BIT INVERSION TECHNIQUES FOR MEMORY SYSTEM REPAIR INDICATIONS | Jul 4, 2024 | Pending |
Array
(
[id] => 19726922
[patent_doc_number] => 20250029673
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-01-23
[patent_title] => BIT INVERSION TECHNIQUES FOR MEMORY SYSTEM REPAIR INDICATIONS
[patent_app_type] => utility
[patent_app_number] => 18/765074
[patent_app_country] => US
[patent_app_date] => 2024-07-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14975
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 170
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18765074
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/765074 | BIT INVERSION TECHNIQUES FOR MEMORY SYSTEM REPAIR INDICATIONS | Jul 4, 2024 | Pending |
Array
(
[id] => 19985698
[patent_doc_number] => 20250123920
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-04-17
[patent_title] => MEMORY DEVICE AND A METHOD OF OPERATING THE SAME DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/764870
[patent_app_country] => US
[patent_app_date] => 2024-07-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4547
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18764870
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/764870 | MEMORY DEVICE AND A METHOD OF OPERATING THE SAME DEVICE | Jul 4, 2024 | Pending |
Array
(
[id] => 19985698
[patent_doc_number] => 20250123920
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-04-17
[patent_title] => MEMORY DEVICE AND A METHOD OF OPERATING THE SAME DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/764870
[patent_app_country] => US
[patent_app_date] => 2024-07-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4547
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18764870
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/764870 | MEMORY DEVICE AND A METHOD OF OPERATING THE SAME DEVICE | Jul 4, 2024 | Pending |
Array
(
[id] => 19530291
[patent_doc_number] => 20240354193
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-24
[patent_title] => Managing Redundancy Levels For Storage Devices During Initial Operation
[patent_app_type] => utility
[patent_app_number] => 18/764022
[patent_app_country] => US
[patent_app_date] => 2024-07-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 17009
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 44
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18764022
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/764022 | Managing Redundancy Levels For Storage Devices During Initial Operation | Jul 2, 2024 | Pending |
Array
(
[id] => 19515438
[patent_doc_number] => 20240347124
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-17
[patent_title] => COUNTING CIRCUIT, SEMICONDUCTOR MEMORY, AND COUNTING METHOD
[patent_app_type] => utility
[patent_app_number] => 18/749644
[patent_app_country] => US
[patent_app_date] => 2024-06-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14696
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18749644
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/749644 | COUNTING CIRCUIT, SEMICONDUCTOR MEMORY, AND COUNTING METHOD | Jun 20, 2024 | Pending |
Array
(
[id] => 19880386
[patent_doc_number] => 20250112643
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-04-03
[patent_title] => APPARATUSES AND METHODS FOR SCALABLE 1-PASS ERROR CORRECTION CODE OPERATIONS
[patent_app_type] => utility
[patent_app_number] => 18/747696
[patent_app_country] => US
[patent_app_date] => 2024-06-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8661
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18747696
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/747696 | APPARATUSES AND METHODS FOR SCALABLE 1-PASS ERROR CORRECTION CODE OPERATIONS | Jun 18, 2024 | Pending |
Array
(
[id] => 19711292
[patent_doc_number] => 20250021434
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-01-16
[patent_title] => DATA PROCESSING APPARATUS, MEMORY FAILURE DETERMINATION METHOD, AND NON-TRANSITORY COMPUTER READABLE RECORDING MEDIUM
[patent_app_type] => utility
[patent_app_number] => 18/747877
[patent_app_country] => US
[patent_app_date] => 2024-06-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5132
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -3
[patent_words_short_claim] => 133
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18747877
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/747877 | DATA PROCESSING APPARATUS, MEMORY FAILURE DETERMINATION METHOD, AND NON-TRANSITORY COMPUTER READABLE RECORDING MEDIUM | Jun 18, 2024 | Pending |
Array
(
[id] => 19711292
[patent_doc_number] => 20250021434
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-01-16
[patent_title] => DATA PROCESSING APPARATUS, MEMORY FAILURE DETERMINATION METHOD, AND NON-TRANSITORY COMPUTER READABLE RECORDING MEDIUM
[patent_app_type] => utility
[patent_app_number] => 18/747877
[patent_app_country] => US
[patent_app_date] => 2024-06-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5132
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -3
[patent_words_short_claim] => 133
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18747877
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/747877 | DATA PROCESSING APPARATUS, MEMORY FAILURE DETERMINATION METHOD, AND NON-TRANSITORY COMPUTER READABLE RECORDING MEDIUM | Jun 18, 2024 | Pending |
Array
(
[id] => 19450308
[patent_doc_number] => 20240310438
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-09-19
[patent_title] => BIT-CORRECTOR CIRCUITS FOR PHOTONIC CIRCUITS WITH CASCADED PHOTONIC GATES
[patent_app_type] => utility
[patent_app_number] => 18/675732
[patent_app_country] => US
[patent_app_date] => 2024-05-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7411
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 132
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18675732
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/675732 | BIT-CORRECTOR CIRCUITS FOR PHOTONIC CIRCUITS WITH CASCADED PHOTONIC GATES | May 27, 2024 | Pending |
Array
(
[id] => 19450308
[patent_doc_number] => 20240310438
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-09-19
[patent_title] => BIT-CORRECTOR CIRCUITS FOR PHOTONIC CIRCUITS WITH CASCADED PHOTONIC GATES
[patent_app_type] => utility
[patent_app_number] => 18/675732
[patent_app_country] => US
[patent_app_date] => 2024-05-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7411
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 132
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18675732
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/675732 | BIT-CORRECTOR CIRCUITS FOR PHOTONIC CIRCUITS WITH CASCADED PHOTONIC GATES | May 27, 2024 | Pending |
Array
(
[id] => 19994549
[patent_doc_number] => 20250132771
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-04-24
[patent_title] => PERFORMING CYCLIC REDUNDANCY CHECKS USING PARALLEL COMPUTING ARCHITECTURES
[patent_app_type] => utility
[patent_app_number] => 18/670615
[patent_app_country] => US
[patent_app_date] => 2024-05-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 51653
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 25
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18670615
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/670615 | PERFORMING CYCLIC REDUNDANCY CHECKS USING PARALLEL COMPUTING ARCHITECTURES | May 20, 2024 | Pending |
Array
(
[id] => 19453760
[patent_doc_number] => 20240313890
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-09-19
[patent_title] => CYCLIC REDUNDANCY CHECK DESIGN FOR COMMON AND PRIVATE TRANSPORT BLOCKS IN RATE SPLITTING TRANSMISSIONS
[patent_app_type] => utility
[patent_app_number] => 18/669271
[patent_app_country] => US
[patent_app_date] => 2024-05-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 29559
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 79
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18669271
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/669271 | CYCLIC REDUNDANCY CHECK DESIGN FOR COMMON AND PRIVATE TRANSPORT BLOCKS IN RATE SPLITTING TRANSMISSIONS | May 19, 2024 | Pending |
Array
(
[id] => 20365951
[patent_doc_number] => 20250355763
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-11-20
[patent_title] => MEMORY DEFECT MANAGEMENT
[patent_app_type] => utility
[patent_app_number] => 18/668854
[patent_app_country] => US
[patent_app_date] => 2024-05-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3473
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 148
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18668854
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/668854 | MEMORY DEFECT MANAGEMENT | May 19, 2024 | Pending |
Array
(
[id] => 20365948
[patent_doc_number] => 20250355760
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-11-20
[patent_title] => VERIFICATION OF DATA TRANSFER SOURCE IN MEMORY DEVICES
[patent_app_type] => utility
[patent_app_number] => 18/668520
[patent_app_country] => US
[patent_app_date] => 2024-05-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 0
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18668520
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/668520 | VERIFICATION OF DATA TRANSFER SOURCE IN MEMORY DEVICES | May 19, 2024 | Pending |
Array
(
[id] => 19453760
[patent_doc_number] => 20240313890
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-09-19
[patent_title] => CYCLIC REDUNDANCY CHECK DESIGN FOR COMMON AND PRIVATE TRANSPORT BLOCKS IN RATE SPLITTING TRANSMISSIONS
[patent_app_type] => utility
[patent_app_number] => 18/669271
[patent_app_country] => US
[patent_app_date] => 2024-05-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 29559
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 79
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18669271
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/669271 | CYCLIC REDUNDANCY CHECK DESIGN FOR COMMON AND PRIVATE TRANSPORT BLOCKS IN RATE SPLITTING TRANSMISSIONS | May 19, 2024 | Pending |
Array
(
[id] => 20061682
[patent_doc_number] => 20250199904
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-06-19
[patent_title] => MEMORY SYSTEM GENERATING PARITY CHECK CODES USING A RANDOMIZER
[patent_app_type] => utility
[patent_app_number] => 18/667767
[patent_app_country] => US
[patent_app_date] => 2024-05-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4573
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 112
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18667767
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/667767 | MEMORY SYSTEM GENERATING PARITY CHECK CODES USING A RANDOMIZER | May 16, 2024 | Pending |