Search

Ana J. Picon-feliciano

Examiner (ID: 3342, Phone: (571)272-5252 , Office: P/2482 )

Most Active Art Unit
2482
Art Unit(s)
2482
Total Applications
463
Issued Applications
290
Pending Applications
56
Abandoned Applications
137

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14472573 [patent_doc_number] => 20190187930 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-20 [patent_title] => THREE-DIMENSIONAL STACKED MEMORY ACCESS OPTIMIZATION [patent_app_type] => utility [patent_app_number] => 15/847957 [patent_app_country] => US [patent_app_date] => 2017-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5251 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15847957 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/847957
Three-dimensional stacked memory access optimization Dec 19, 2017 Issued
Array ( [id] => 15317295 [patent_doc_number] => 10523369 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-31 [patent_title] => Mutual-information based recursive polar code construction [patent_app_type] => utility [patent_app_number] => 15/849034 [patent_app_country] => US [patent_app_date] => 2017-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 23 [patent_no_of_words] => 22114 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15849034 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/849034
Mutual-information based recursive polar code construction Dec 19, 2017 Issued
Array ( [id] => 12611985 [patent_doc_number] => 20180095825 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-05 [patent_title] => SELECTING RETRIEVAL LOCATIONS IN A DISPERSED STORAGE NETWORK [patent_app_type] => utility [patent_app_number] => 15/832316 [patent_app_country] => US [patent_app_date] => 2017-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7111 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15832316 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/832316
Selecting retrieval locations in a dispersed storage network Dec 4, 2017 Issued
Array ( [id] => 13614865 [patent_doc_number] => 20180358983 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-13 [patent_title] => LOW DENSITY PARITY CHECK DECODER USING BINARY LOGARITHM AND DECODING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 15/803073 [patent_app_country] => US [patent_app_date] => 2017-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6812 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15803073 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/803073
Low density parity check decoder using binary logarithm and decoding method thereof Nov 2, 2017 Issued
Array ( [id] => 12718675 [patent_doc_number] => 20180131391 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-10 [patent_title] => EFFICIENT LIST DECODING OF LDPC CODES [patent_app_type] => utility [patent_app_number] => 15/802163 [patent_app_country] => US [patent_app_date] => 2017-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13473 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -28 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15802163 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/802163
Efficient list decoding of LDPC codes Nov 1, 2017 Issued
Array ( [id] => 12718678 [patent_doc_number] => 20180131392 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-10 [patent_title] => NR LDPC With Interleaver [patent_app_type] => utility [patent_app_number] => 15/802265 [patent_app_country] => US [patent_app_date] => 2017-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4453 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15802265 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/802265
NR LDPC With Interleaver Nov 1, 2017 Abandoned
Array ( [id] => 13431111 [patent_doc_number] => 20180267098 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-20 [patent_title] => MAPPING PHYSICAL SHIFT FAILURES TO SCAN CELLS FOR DETECTING PHYSICAL FAULTS IN INTEGRATED CIRCUITS [patent_app_type] => utility [patent_app_number] => 15/796423 [patent_app_country] => US [patent_app_date] => 2017-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9328 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15796423 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/796423
Mapping physical shift failures to scan cells for detecting physical faults in integrated circuits Oct 26, 2017 Issued
Array ( [id] => 14952453 [patent_doc_number] => 10437490 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-08 [patent_title] => Reading of start-up information from different memory regions of a memory system [patent_app_type] => utility [patent_app_number] => 15/786959 [patent_app_country] => US [patent_app_date] => 2017-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 23 [patent_no_of_words] => 5268 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15786959 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/786959
Reading of start-up information from different memory regions of a memory system Oct 17, 2017 Issued
Array ( [id] => 14187727 [patent_doc_number] => 20190113568 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-18 [patent_title] => Multi-Processor Core Device With MBIST [patent_app_type] => utility [patent_app_number] => 15/785792 [patent_app_country] => US [patent_app_date] => 2017-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5983 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15785792 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/785792
Multi-processor core device with MBIST Oct 16, 2017 Issued
Array ( [id] => 15476875 [patent_doc_number] => 10554334 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-04 [patent_title] => Nominally unguaranteed error-detection codes for sub-data packets [patent_app_type] => utility [patent_app_number] => 15/786291 [patent_app_country] => US [patent_app_date] => 2017-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4958 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15786291 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/786291
Nominally unguaranteed error-detection codes for sub-data packets Oct 16, 2017 Issued
Array ( [id] => 15887147 [patent_doc_number] => 10649918 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-12 [patent_title] => Dynamic reconfiguration and management of memory using field programmable gate arrays [patent_app_type] => utility [patent_app_number] => 15/718640 [patent_app_country] => US [patent_app_date] => 2017-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9221 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15718640 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/718640
Dynamic reconfiguration and management of memory using field programmable gate arrays Sep 27, 2017 Issued
Array ( [id] => 12244059 [patent_doc_number] => 20180076923 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-15 [patent_title] => 'Combined Coding Design For Efficient Codeblock Extension' [patent_app_type] => utility [patent_app_number] => 15/701431 [patent_app_country] => US [patent_app_date] => 2017-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5908 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15701431 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/701431
Combined coding design for efficient codeblock extension Sep 10, 2017 Issued
Array ( [id] => 14824987 [patent_doc_number] => 10409500 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-10 [patent_title] => Multiple indirection granularities for mass storage devices [patent_app_type] => utility [patent_app_number] => 15/699930 [patent_app_country] => US [patent_app_date] => 2017-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8872 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15699930 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/699930
Multiple indirection granularities for mass storage devices Sep 7, 2017 Issued
Array ( [id] => 15489503 [patent_doc_number] => 10560120 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-11 [patent_title] => Elementary check node processing for syndrome computation for non-binary LDPC codes decoding [patent_app_type] => utility [patent_app_number] => 15/694062 [patent_app_country] => US [patent_app_date] => 2017-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 15069 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15694062 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/694062
Elementary check node processing for syndrome computation for non-binary LDPC codes decoding Aug 31, 2017 Issued
Array ( [id] => 13447311 [patent_doc_number] => 20180275198 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-27 [patent_title] => SEMICONDUCTOR INTEGRATED CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT DIAGNOSIS METHOD [patent_app_type] => utility [patent_app_number] => 15/691121 [patent_app_country] => US [patent_app_date] => 2017-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9782 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15691121 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/691121
Semiconductor integrated circuit and semiconductor integrated circuit diagnosis method Aug 29, 2017 Issued
Array ( [id] => 14493509 [patent_doc_number] => 10333559 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-25 [patent_title] => Hybrid decoding method and gigabit Ethernet receiver using the same [patent_app_type] => utility [patent_app_number] => 15/690390 [patent_app_country] => US [patent_app_date] => 2017-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4807 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 352 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15690390 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/690390
Hybrid decoding method and gigabit Ethernet receiver using the same Aug 29, 2017 Issued
Array ( [id] => 13708807 [patent_doc_number] => 20170365358 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-21 [patent_title] => METHODS OF OPERATING A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 15/689459 [patent_app_country] => US [patent_app_date] => 2017-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5757 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15689459 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/689459
Methods of operating a memory device Aug 28, 2017 Issued
Array ( [id] => 17100930 [patent_doc_number] => 20210288721 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-16 [patent_title] => OPTICAL RECEPTION APPARATUS AND CONTROL METHOD [patent_app_type] => utility [patent_app_number] => 16/338733 [patent_app_country] => US [patent_app_date] => 2017-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4847 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16338733 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/338733
Optical reception apparatus and control method Aug 24, 2017 Issued
Array ( [id] => 13720073 [patent_doc_number] => 20170370991 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-28 [patent_title] => SCHEME TO MEASURE INDIVIDUALLY RISE AND FALL DELAYS OF NON INVERTING LOGIC CELLS [patent_app_type] => utility [patent_app_number] => 15/678016 [patent_app_country] => US [patent_app_date] => 2017-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7623 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15678016 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/678016
Scheme to measure individually rise and fall delays of non-inverting logic cells Aug 14, 2017 Issued
Array ( [id] => 12155399 [patent_doc_number] => 20180026663 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-25 [patent_title] => 'LOW COMPLEXITY RATE MATCHING FOR POLAR CODES' [patent_app_type] => utility [patent_app_number] => 15/653048 [patent_app_country] => US [patent_app_date] => 2017-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 10031 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15653048 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/653048
Low complexity rate matching for polar codes Jul 17, 2017 Issued
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