Search

Ana J. Picon-feliciano

Examiner (ID: 3342, Phone: (571)272-5252 , Office: P/2482 )

Most Active Art Unit
2482
Art Unit(s)
2482
Total Applications
463
Issued Applications
290
Pending Applications
56
Abandoned Applications
137

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14673403 [patent_doc_number] => 10374630 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-06 [patent_title] => Low-density parity check decoder, a storage device including the same, and a method [patent_app_type] => utility [patent_app_number] => 15/652260 [patent_app_country] => US [patent_app_date] => 2017-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 6555 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15652260 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/652260
Low-density parity check decoder, a storage device including the same, and a method Jul 17, 2017 Issued
Array ( [id] => 12153615 [patent_doc_number] => 20180024879 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-25 [patent_title] => 'DECODER USING LOW-DENSITY PARITY-CHECK CODE AND MEMORY CONTROLLER INCLUDING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/652521 [patent_app_country] => US [patent_app_date] => 2017-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8223 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15652521 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/652521
Decoder using low-density parity-check code and memory controller including the same Jul 17, 2017 Issued
Array ( [id] => 12209053 [patent_doc_number] => 20180054278 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-22 [patent_title] => 'REDUCED-STAGE POLAR DECODING' [patent_app_type] => utility [patent_app_number] => 15/651390 [patent_app_country] => US [patent_app_date] => 2017-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 15306 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15651390 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/651390
Reduced-stage polar decoding Jul 16, 2017 Issued
Array ( [id] => 14397265 [patent_doc_number] => 10311920 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-04 [patent_title] => Apparatus and method for controlling memory device [patent_app_type] => utility [patent_app_number] => 15/651084 [patent_app_country] => US [patent_app_date] => 2017-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 22 [patent_no_of_words] => 15187 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15651084 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/651084
Apparatus and method for controlling memory device Jul 16, 2017 Issued
Array ( [id] => 15582309 [patent_doc_number] => 10581559 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-03 [patent_title] => User Equipment, base stations and methods [patent_app_type] => utility [patent_app_number] => 15/649894 [patent_app_country] => US [patent_app_date] => 2017-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 21485 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15649894 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/649894
User Equipment, base stations and methods Jul 13, 2017 Issued
Array ( [id] => 15141017 [patent_doc_number] => 10484007 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-19 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 15/628857 [patent_app_country] => US [patent_app_date] => 2017-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3387 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15628857 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/628857
Semiconductor device Jun 20, 2017 Issued
Array ( [id] => 16959728 [patent_doc_number] => 11063613 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-13 [patent_title] => Early termination of successive cancellation list decoding [patent_app_type] => utility [patent_app_number] => 16/605911 [patent_app_country] => US [patent_app_date] => 2017-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 19399 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16605911 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/605911
Early termination of successive cancellation list decoding May 14, 2017 Issued
Array ( [id] => 17138261 [patent_doc_number] => 11139834 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-05 [patent_title] => Decoder for a family of rate compatible low-density parity check (LDPC) codes [patent_app_type] => utility [patent_app_number] => 16/092813 [patent_app_country] => US [patent_app_date] => 2017-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 6187 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 1142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16092813 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/092813
Decoder for a family of rate compatible low-density parity check (LDPC) codes Apr 12, 2017 Issued
Array ( [id] => 13723673 [patent_doc_number] => 20170372792 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-28 [patent_title] => TEST APPARATUS, MEMORY TEST SYSTEM, AND TEST METHOD [patent_app_type] => utility [patent_app_number] => 15/473987 [patent_app_country] => US [patent_app_date] => 2017-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3667 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15473987 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/473987
TEST APPARATUS, MEMORY TEST SYSTEM, AND TEST METHOD Mar 29, 2017 Abandoned
Array ( [id] => 14393471 [patent_doc_number] => 10310012 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-04 [patent_title] => Lightweight, low overhead debug bus [patent_app_type] => utility [patent_app_number] => 15/473593 [patent_app_country] => US [patent_app_date] => 2017-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6192 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15473593 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/473593
Lightweight, low overhead debug bus Mar 28, 2017 Issued
Array ( [id] => 14362811 [patent_doc_number] => 10302700 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-28 [patent_title] => Test circuit to debug missed test clock pulses [patent_app_type] => utility [patent_app_number] => 15/473100 [patent_app_country] => US [patent_app_date] => 2017-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2461 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15473100 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/473100
Test circuit to debug missed test clock pulses Mar 28, 2017 Issued
Array ( [id] => 13465291 [patent_doc_number] => 20180284188 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-04 [patent_title] => SINGLE CIRCUIT FAULT DETECTION [patent_app_type] => utility [patent_app_number] => 15/471539 [patent_app_country] => US [patent_app_date] => 2017-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6610 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15471539 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/471539
Single circuit fault detection Mar 27, 2017 Issued
Array ( [id] => 12220821 [patent_doc_number] => 20180059181 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-01 [patent_title] => 'SEMICONDUCTOR DEVICE METHOD RELATING TO LATCH CIRCUIT TESTING' [patent_app_type] => utility [patent_app_number] => 15/471866 [patent_app_country] => US [patent_app_date] => 2017-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4477 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15471866 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/471866
Semiconductor device method relating to latch circuit testing Mar 27, 2017 Issued
Array ( [id] => 12891871 [patent_doc_number] => 20180189132 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-05 [patent_title] => MEMORY APPARATUS FOR IN-CHIP ERROR CORRECTION [patent_app_type] => utility [patent_app_number] => 15/470657 [patent_app_country] => US [patent_app_date] => 2017-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5748 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15470657 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/470657
Memory apparatus for in-chip error correction Mar 26, 2017 Issued
Array ( [id] => 14393473 [patent_doc_number] => 10310013 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-04 [patent_title] => Test mode isolation and power reduction in embedded core-based digital systems of integrated circuits (ICs) with multiple power domains [patent_app_type] => utility [patent_app_number] => 15/470880 [patent_app_country] => US [patent_app_date] => 2017-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 9325 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15470880 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/470880
Test mode isolation and power reduction in embedded core-based digital systems of integrated circuits (ICs) with multiple power domains Mar 26, 2017 Issued
Array ( [id] => 12207506 [patent_doc_number] => 20180052732 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-22 [patent_title] => 'SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SYSTEM' [patent_app_type] => utility [patent_app_number] => 15/469047 [patent_app_country] => US [patent_app_date] => 2017-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7441 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15469047 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/469047
SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SYSTEM Mar 23, 2017 Abandoned
Array ( [id] => 14399295 [patent_doc_number] => 10312943 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-04 [patent_title] => Error correction code in memory [patent_app_type] => utility [patent_app_number] => 15/468619 [patent_app_country] => US [patent_app_date] => 2017-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6644 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15468619 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/468619
Error correction code in memory Mar 23, 2017 Issued
Array ( [id] => 17289473 [patent_doc_number] => 11206042 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-21 [patent_title] => Layered decoding method for LDPC code and device therefor [patent_app_type] => utility [patent_app_number] => 16/492458 [patent_app_country] => US [patent_app_date] => 2017-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 21 [patent_no_of_words] => 9821 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16492458 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/492458
Layered decoding method for LDPC code and device therefor Mar 8, 2017 Issued
Array ( [id] => 14553845 [patent_doc_number] => 10345375 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-09 [patent_title] => Test method and test apparatus for testing a plurality of blocks in a circuit [patent_app_type] => utility [patent_app_number] => 15/447178 [patent_app_country] => US [patent_app_date] => 2017-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 8620 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15447178 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/447178
Test method and test apparatus for testing a plurality of blocks in a circuit Mar 1, 2017 Issued
Array ( [id] => 13332711 [patent_doc_number] => 20180217893 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-02 [patent_title] => MEMORY DEVICE AND CONTROL METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 15/420367 [patent_app_country] => US [patent_app_date] => 2017-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5569 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15420367 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/420367
Memory device and control method thereof Jan 30, 2017 Issued
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