
Ana J. Picon-feliciano
Examiner (ID: 3342, Phone: (571)272-5252 , Office: P/2482 )
| Most Active Art Unit | 2482 |
| Art Unit(s) | 2482 |
| Total Applications | 463 |
| Issued Applications | 290 |
| Pending Applications | 56 |
| Abandoned Applications | 137 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 12094476
[patent_doc_number] => 20170351569
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-12-07
[patent_title] => 'READING-THRESHOLD SETTING BASED ON DATA ENCODED WITH A MULTI-COMPONENT CODE'
[patent_app_type] => utility
[patent_app_number] => 15/169825
[patent_app_country] => US
[patent_app_date] => 2016-06-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 7130
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15169825
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/169825 | Reading-threshold setting based on data encoded with a multi-component code | May 31, 2016 | Issued |
Array
(
[id] => 11938599
[patent_doc_number] => 20170242749
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-08-24
[patent_title] => 'SEMICONDUCTOR DEVICE AND DRIVING METHOD THEREOF'
[patent_app_type] => utility
[patent_app_number] => 15/170446
[patent_app_country] => US
[patent_app_date] => 2016-06-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 7516
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15170446
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/170446 | Semiconductor device and driving method thereof | May 31, 2016 | Issued |
Array
(
[id] => 11458319
[patent_doc_number] => 20170052225
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-02-23
[patent_title] => 'SEMICONDUCTOR CHIP, TEST SYSTEM, AND METHOD OF TESTING THE SEMICONDUCTOR CHIP'
[patent_app_type] => utility
[patent_app_number] => 15/170940
[patent_app_country] => US
[patent_app_date] => 2016-06-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 4856
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15170940
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/170940 | Semiconductor chip, test system, and method of testing the semiconductor chip | May 31, 2016 | Issued |
Array
(
[id] => 11072183
[patent_doc_number] => 20160269147
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-09-15
[patent_title] => 'BITWISE OPERATIONS AND APPARATUS IN A MULTI-LEVEL SYSTEM'
[patent_app_type] => utility
[patent_app_number] => 15/160322
[patent_app_country] => US
[patent_app_date] => 2016-05-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 20084
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15160322
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/160322 | Bitwise operations and apparatus in a multi-level system | May 19, 2016 | Issued |
Array
(
[id] => 12741274
[patent_doc_number] => 20180138925
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-05-17
[patent_title] => DECODING APPARATUS, DECODING METHOD AND PROGRAM
[patent_app_type] => utility
[patent_app_number] => 15/572050
[patent_app_country] => US
[patent_app_date] => 2016-05-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6536
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -5
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15572050
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/572050 | Decoding apparatus, decoding method and program | May 10, 2016 | Issued |
Array
(
[id] => 11126088
[patent_doc_number] => 20160323063
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-11-03
[patent_title] => 'Bundled Forward Error Correction (FEC) for Multiple Sequenced Flows'
[patent_app_type] => utility
[patent_app_number] => 15/138451
[patent_app_country] => US
[patent_app_date] => 2016-04-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 9775
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15138451
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/138451 | Bundled Forward Error Correction (FEC) for Multiple Sequenced Flows | Apr 25, 2016 | Abandoned |
Array
(
[id] => 12003530
[patent_doc_number] => 20170307685
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-10-26
[patent_title] => 'TESTING MECHANISM FOR A PROXIMITY FAIL PROBABILITY OF DEFECTS ACROSS INTEGRATED CHIPS'
[patent_app_type] => utility
[patent_app_number] => 15/138906
[patent_app_country] => US
[patent_app_date] => 2016-04-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 5454
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15138906
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/138906 | Testing mechanism for a proximity fail probability of defects across integrated chips | Apr 25, 2016 | Issued |
Array
(
[id] => 11118790
[patent_doc_number] => 20160315764
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-10-27
[patent_title] => 'FAULT DETECTION FOR SYSTEMS IMPLEMENTING A BLOCK CIPHER'
[patent_app_type] => utility
[patent_app_number] => 15/137499
[patent_app_country] => US
[patent_app_date] => 2016-04-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3313
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15137499
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/137499 | FAULT DETECTION FOR SYSTEMS IMPLEMENTING A BLOCK CIPHER | Apr 24, 2016 | Abandoned |
Array
(
[id] => 11272482
[patent_doc_number] => 20160335029
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-11-17
[patent_title] => 'MEMORY APPARATUS, MEMORY SYSTEM AND MEMORY CONTROLLING METHOD'
[patent_app_type] => utility
[patent_app_number] => 15/137031
[patent_app_country] => US
[patent_app_date] => 2016-04-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 5799
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15137031
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/137031 | Memory apparatus, memory system and memory controlling method | Apr 24, 2016 | Issued |
Array
(
[id] => 12569280
[patent_doc_number] => 10018674
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-07-10
[patent_title] => V
[patent_app_type] => utility
[patent_app_number] => 15/072280
[patent_app_country] => US
[patent_app_date] => 2016-03-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 7792
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 144
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15072280
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/072280 | V | Mar 15, 2016 | Issued |
Array
(
[id] => 12193930
[patent_doc_number] => 09897653
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-02-20
[patent_title] => 'Scan chain circuit supporting logic self test pattern injection during run time'
[patent_app_type] => utility
[patent_app_number] => 15/071342
[patent_app_country] => US
[patent_app_date] => 2016-03-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 4714
[patent_no_of_claims] => 37
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 157
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15071342
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/071342 | Scan chain circuit supporting logic self test pattern injection during run time | Mar 15, 2016 | Issued |
Array
(
[id] => 11437983
[patent_doc_number] => 20170039003
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-02-09
[patent_title] => 'MEMORY CONTROLLER AND SEMICONDUCTOR MEMORY DEVICE'
[patent_app_type] => utility
[patent_app_number] => 15/058624
[patent_app_country] => US
[patent_app_date] => 2016-03-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 10521
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15058624
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/058624 | Memory controller and semiconductor memory device | Mar 1, 2016 | Issued |
Array
(
[id] => 14770811
[patent_doc_number] => 10396818
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-08-27
[patent_title] => Transmitter and segmentation method thereof
[patent_app_type] => utility
[patent_app_number] => 15/058255
[patent_app_country] => US
[patent_app_date] => 2016-03-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 29
[patent_figures_cnt] => 29
[patent_no_of_words] => 31022
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 305
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15058255
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/058255 | Transmitter and segmentation method thereof | Mar 1, 2016 | Issued |
Array
(
[id] => 11424705
[patent_doc_number] => 20170032850
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-02-02
[patent_title] => 'SEMICONDUCTOR MEMORY APPARATUS AND TEST METHOD THEREOF'
[patent_app_type] => utility
[patent_app_number] => 15/049900
[patent_app_country] => US
[patent_app_date] => 2016-02-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3555
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15049900
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/049900 | SEMICONDUCTOR MEMORY APPARATUS AND TEST METHOD THEREOF | Feb 21, 2016 | Abandoned |
Array
(
[id] => 11272601
[patent_doc_number] => 20160335148
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-11-17
[patent_title] => 'LIVE ERROR RECOVERY'
[patent_app_type] => utility
[patent_app_number] => 15/042463
[patent_app_country] => US
[patent_app_date] => 2016-02-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 13430
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15042463
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/042463 | Live error recovery | Feb 11, 2016 | Issued |
Array
(
[id] => 11476710
[patent_doc_number] => 20170063493
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-03-02
[patent_title] => 'METHODS AND CIRCUITS FOR PERFORMING CYCLIC REDUNDANCY CHECK (CRC) OF AN INPUT DATA STREAM'
[patent_app_type] => utility
[patent_app_number] => 15/042404
[patent_app_country] => US
[patent_app_date] => 2016-02-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 8188
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15042404
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/042404 | METHODS AND CIRCUITS FOR PERFORMING CYCLIC REDUNDANCY CHECK (CRC) OF AN INPUT DATA STREAM | Feb 11, 2016 | Abandoned |
Array
(
[id] => 13142397
[patent_doc_number] => 10088525
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-10-02
[patent_title] => Non-interleaved scan operation for achieving higher scan throughput in presence of slower scan outputs
[patent_app_type] => utility
[patent_app_number] => 15/042130
[patent_app_country] => US
[patent_app_date] => 2016-02-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 5028
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 179
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15042130
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/042130 | Non-interleaved scan operation for achieving higher scan throughput in presence of slower scan outputs | Feb 10, 2016 | Issued |
Array
(
[id] => 13017173
[patent_doc_number] => 10031701
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-07-24
[patent_title] => Hierarchical processing for extended product codes
[patent_app_type] => utility
[patent_app_number] => 15/019633
[patent_app_country] => US
[patent_app_date] => 2016-02-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 31
[patent_figures_cnt] => 40
[patent_no_of_words] => 16678
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 294
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15019633
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/019633 | Hierarchical processing for extended product codes | Feb 8, 2016 | Issued |
Array
(
[id] => 12108874
[patent_doc_number] => 09865362
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2018-01-09
[patent_title] => 'Method and apparatus for testing error correction code (ECC) logic and physical memory onboard a manufactured integrated circuit (IC)'
[patent_app_type] => utility
[patent_app_number] => 15/019504
[patent_app_country] => US
[patent_app_date] => 2016-02-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 11616
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 245
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15019504
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/019504 | Method and apparatus for testing error correction code (ECC) logic and physical memory onboard a manufactured integrated circuit (IC) | Feb 8, 2016 | Issued |
Array
(
[id] => 14065189
[patent_doc_number] => 10236910
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-03-19
[patent_title] => Iterative decoding method of LFSR sequences with a low false-alarm probability
[patent_app_type] => utility
[patent_app_number] => 15/017965
[patent_app_country] => US
[patent_app_date] => 2016-02-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 5027
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 426
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15017965
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/017965 | Iterative decoding method of LFSR sequences with a low false-alarm probability | Feb 7, 2016 | Issued |