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Ana J. Picon-feliciano

Examiner (ID: 3342, Phone: (571)272-5252 , Office: P/2482 )

Most Active Art Unit
2482
Art Unit(s)
2482
Total Applications
463
Issued Applications
290
Pending Applications
56
Abandoned Applications
137

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19436816 [patent_doc_number] => 20240305314 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-12 [patent_title] => SPECTRAL UNMIXING COMBINED WITH DECODING FOR SUPER-MULTIPLEXED IN SITU ANALYSIS [patent_app_type] => utility [patent_app_number] => 18/660149 [patent_app_country] => US [patent_app_date] => 2024-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 36201 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18660149 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/660149
SPECTRAL UNMIXING COMBINED WITH DECODING FOR SUPER-MULTIPLEXED IN SITU ANALYSIS May 8, 2024 Pending
Array ( [id] => 19992669 [patent_doc_number] => 20250130891 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-24 [patent_title] => SEMICONDUCTOR MEMORY DEVICES WITH ERROR CORRECTION [patent_app_type] => utility [patent_app_number] => 18/657360 [patent_app_country] => US [patent_app_date] => 2024-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8621 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18657360 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/657360
SEMICONDUCTOR MEMORY DEVICES WITH ERROR CORRECTION May 6, 2024 Pending
Array ( [id] => 20242860 [patent_doc_number] => 12423179 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-23 [patent_title] => Stack memory devices communicating via packets [patent_app_type] => utility [patent_app_number] => 18/654843 [patent_app_country] => US [patent_app_date] => 2024-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3401 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18654843 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/654843
Stack memory devices communicating via packets May 2, 2024 Issued
Array ( [id] => 19532769 [patent_doc_number] => 20240356671 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-24 [patent_title] => BIT ERROR CORRECTION FOR BLUETOOTH LOW ENERGY [patent_app_type] => utility [patent_app_number] => 18/649402 [patent_app_country] => US [patent_app_date] => 2024-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9742 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18649402 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/649402
BIT ERROR CORRECTION FOR BLUETOOTH LOW ENERGY Apr 28, 2024 Pending
Array ( [id] => 19758741 [patent_doc_number] => 20250047306 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-06 [patent_title] => SYSTEM AND METHOD FOR LOW DENSITY PARITY CHECK (LDPC) CODE WITH 3/4 CODE RATE [patent_app_type] => utility [patent_app_number] => 18/647710 [patent_app_country] => US [patent_app_date] => 2024-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14378 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18647710 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/647710
SYSTEM AND METHOD FOR LOW DENSITY PARITY CHECK (LDPC) CODE WITH 3/4 CODE RATE Apr 25, 2024 Pending
Array ( [id] => 20064282 [patent_doc_number] => 20250202504 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-19 [patent_title] => SYSTEMS AND METHODS FOR BLOCK-KRONECKER BASED LOW DENSITY PARITY CHECK (LDPC) CODE WITH 5/6 CODE RATE [patent_app_type] => utility [patent_app_number] => 18/647780 [patent_app_country] => US [patent_app_date] => 2024-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14344 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18647780 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/647780
SYSTEMS AND METHODS FOR BLOCK-KRONECKER BASED LOW DENSITY PARITY CHECK (LDPC) CODE WITH 5/6 CODE RATE Apr 25, 2024 Pending
Array ( [id] => 20064282 [patent_doc_number] => 20250202504 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-19 [patent_title] => SYSTEMS AND METHODS FOR BLOCK-KRONECKER BASED LOW DENSITY PARITY CHECK (LDPC) CODE WITH 5/6 CODE RATE [patent_app_type] => utility [patent_app_number] => 18/647780 [patent_app_country] => US [patent_app_date] => 2024-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14344 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18647780 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/647780
SYSTEMS AND METHODS FOR BLOCK-KRONECKER BASED LOW DENSITY PARITY CHECK (LDPC) CODE WITH 5/6 CODE RATE Apr 25, 2024 Pending
Array ( [id] => 20064282 [patent_doc_number] => 20250202504 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-19 [patent_title] => SYSTEMS AND METHODS FOR BLOCK-KRONECKER BASED LOW DENSITY PARITY CHECK (LDPC) CODE WITH 5/6 CODE RATE [patent_app_type] => utility [patent_app_number] => 18/647780 [patent_app_country] => US [patent_app_date] => 2024-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14344 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18647780 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/647780
SYSTEMS AND METHODS FOR BLOCK-KRONECKER BASED LOW DENSITY PARITY CHECK (LDPC) CODE WITH 5/6 CODE RATE Apr 25, 2024 Pending
Array ( [id] => 20312573 [patent_doc_number] => 20250330202 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-23 [patent_title] => Forward Error Correction Synchronization Method and Forward Error Correction Synchronization System Capable of recovering Synchronization of Forward Error Correction Blocks [patent_app_type] => utility [patent_app_number] => 18/642726 [patent_app_country] => US [patent_app_date] => 2024-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18642726 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/642726
Forward error correction synchronization method and forward error correction synchronization system capable of recovering synchronization of forward error correction blocks Apr 21, 2024 Issued
Array ( [id] => 20000718 [patent_doc_number] => 20250138940 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-01 [patent_title] => NONVOLATILE MEMORY [patent_app_type] => utility [patent_app_number] => 18/639856 [patent_app_country] => US [patent_app_date] => 2024-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9425 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18639856 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/639856
NONVOLATILE MEMORY Apr 17, 2024 Pending
Array ( [id] => 19532664 [patent_doc_number] => 20240356566 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-24 [patent_title] => FAST MULTI-PAYLOAD-LENGTH ERROR-CORRECTING SYSTEM AND METHODS [patent_app_type] => utility [patent_app_number] => 18/631840 [patent_app_country] => US [patent_app_date] => 2024-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12911 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18631840 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/631840
FAST MULTI-PAYLOAD-LENGTH ERROR-CORRECTING SYSTEM AND METHODS Apr 9, 2024 Pending
Array ( [id] => 19532665 [patent_doc_number] => 20240356567 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-24 [patent_title] => FAST MULTI-PAYLOAD-LENGTH ERROR-CORRECTING SYSTEM AND METHODS [patent_app_type] => utility [patent_app_number] => 18/631870 [patent_app_country] => US [patent_app_date] => 2024-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12726 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18631870 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/631870
FAST MULTI-PAYLOAD-LENGTH ERROR-CORRECTING SYSTEM AND METHODS Apr 9, 2024 Pending
Array ( [id] => 20236480 [patent_doc_number] => 20250293799 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-18 [patent_title] => ELECTRONIC DEVICE AND OPERATION METHOD THEREFOR [patent_app_type] => utility [patent_app_number] => 18/631286 [patent_app_country] => US [patent_app_date] => 2024-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6505 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18631286 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/631286
ELECTRONIC DEVICE AND OPERATION METHOD THEREFOR Apr 9, 2024 Pending
Array ( [id] => 19347412 [patent_doc_number] => 20240256375 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => AUTOMATED OPTIMIZATION OF ERROR-HANDLING FLOWS IN MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/631928 [patent_app_country] => US [patent_app_date] => 2024-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10389 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18631928 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/631928
AUTOMATED OPTIMIZATION OF ERROR-HANDLING FLOWS IN MEMORY DEVICES Apr 9, 2024 Issued
Array ( [id] => 19501008 [patent_doc_number] => 20240340026 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-10 [patent_title] => LOW-DENSITY PARITY-CHECK (LDPC) ENCODING AND SIGNALING IN A WIRELESS NETWORK [patent_app_type] => utility [patent_app_number] => 18/629795 [patent_app_country] => US [patent_app_date] => 2024-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12642 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18629795 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/629795
LOW-DENSITY PARITY-CHECK (LDPC) ENCODING AND SIGNALING IN A WIRELESS NETWORK Apr 7, 2024 Pending
Array ( [id] => 20070730 [patent_doc_number] => 20250208952 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-26 [patent_title] => BIT ERROR DETECTION IN A COMPUTE-IN-MEMORY SYSTEM, METHOD OF OPERATING SAME, AND METHOD OF MANUFACTURING SAME [patent_app_type] => utility [patent_app_number] => 18/618207 [patent_app_country] => US [patent_app_date] => 2024-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18631 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18618207 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/618207
BIT ERROR DETECTION IN A COMPUTE-IN-MEMORY SYSTEM, METHOD OF OPERATING SAME, AND METHOD OF MANUFACTURING SAME Mar 26, 2024 Pending
Array ( [id] => 19322211 [patent_doc_number] => 20240243759 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-18 [patent_title] => APPARATUS AND METHOD FOR GENERATING A FROZEN SET ASSOCIATED WITH A POLAR CODE [patent_app_type] => utility [patent_app_number] => 18/613097 [patent_app_country] => US [patent_app_date] => 2024-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12651 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18613097 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/613097
APPARATUS AND METHOD FOR GENERATING A FROZEN SET ASSOCIATED WITH A POLAR CODE Mar 20, 2024 Pending
Array ( [id] => 19283887 [patent_doc_number] => 20240220363 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => CONTROLLER AND MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/602031 [patent_app_country] => US [patent_app_date] => 2024-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6247 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18602031 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/602031
Controller and memory system Mar 11, 2024 Issued
Array ( [id] => 20266833 [patent_doc_number] => 12437829 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-07 [patent_title] => Apparatuses, systems, and methods for storing error information and providing recommendations based on same [patent_app_type] => utility [patent_app_number] => 18/598899 [patent_app_country] => US [patent_app_date] => 2024-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7854 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18598899 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/598899
Apparatuses, systems, and methods for storing error information and providing recommendations based on same Mar 6, 2024 Issued
Array ( [id] => 20375908 [patent_doc_number] => 12483355 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-25 [patent_title] => Puncturing-based 240 MHz transmission [patent_app_type] => utility [patent_app_number] => 18/594629 [patent_app_country] => US [patent_app_date] => 2024-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 22692 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18594629 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/594629
Puncturing-based 240 MHz transmission Mar 3, 2024 Issued
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