Search

Ana J. Picon-feliciano

Examiner (ID: 3342, Phone: (571)272-5252 , Office: P/2482 )

Most Active Art Unit
2482
Art Unit(s)
2482
Total Applications
463
Issued Applications
290
Pending Applications
56
Abandoned Applications
137

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10807901 [patent_doc_number] => 20160154060 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-02 [patent_title] => 'Automated Test Equipment, Instruction Provider for Providing a Sequence of Instructions, Method of Providing Signal to a Device Under Test, Method for Providing a Sequence of Instructions and Test System' [patent_app_type] => utility [patent_app_number] => 15/016640 [patent_app_country] => US [patent_app_date] => 2016-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6762 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15016640 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/016640
Automated test equipment, instruction provider for providing a sequence of instructions, method of providing signal to a device under test, method for providing a sequence of instructions and test system Feb 4, 2016 Issued
Array ( [id] => 11855655 [patent_doc_number] => 20170230147 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-10 [patent_title] => 'METHOD AND APPARATUS FOR IMPLEMENTING A RETRANSMISSION SCHEME' [patent_app_type] => utility [patent_app_number] => 15/016931 [patent_app_country] => US [patent_app_date] => 2016-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6108 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15016931 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/016931
METHOD AND APPARATUS FOR IMPLEMENTING A RETRANSMISSION SCHEME Feb 4, 2016 Abandoned
Array ( [id] => 12931042 [patent_doc_number] => 09829536 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-11-28 [patent_title] => Performing on-chip partial good die identification [patent_app_type] => utility [patent_app_number] => 15/015100 [patent_app_country] => US [patent_app_date] => 2016-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 7477 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15015100 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/015100
Performing on-chip partial good die identification Feb 2, 2016 Issued
Array ( [id] => 13003983 [patent_doc_number] => 10025660 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-17 [patent_title] => Data reading method, memory control circuit unit and memory storage apparatus [patent_app_type] => utility [patent_app_number] => 15/009771 [patent_app_country] => US [patent_app_date] => 2016-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 9359 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 354 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15009771 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/009771
Data reading method, memory control circuit unit and memory storage apparatus Jan 27, 2016 Issued
Array ( [id] => 12213285 [patent_doc_number] => 09910086 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-06 [patent_title] => 'Test IP-based A.T.E. instrument architecture' [patent_app_type] => utility [patent_app_number] => 15/008594 [patent_app_country] => US [patent_app_date] => 2016-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 20 [patent_no_of_words] => 7785 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 392 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15008594 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/008594
Test IP-based A.T.E. instrument architecture Jan 27, 2016 Issued
Array ( [id] => 13086373 [patent_doc_number] => 10063262 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-08-28 [patent_title] => Non-concatenated FEC codes for ultra-high speed optical transport networks [patent_app_type] => utility [patent_app_number] => 15/000978 [patent_app_country] => US [patent_app_date] => 2016-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 22 [patent_no_of_words] => 9870 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 298 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15000978 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/000978
Non-concatenated FEC codes for ultra-high speed optical transport networks Jan 18, 2016 Issued
Array ( [id] => 12206978 [patent_doc_number] => 20180052204 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-22 [patent_title] => 'FPGA Clock Signal Self-detection Method' [patent_app_type] => utility [patent_app_number] => 15/556652 [patent_app_country] => US [patent_app_date] => 2016-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 736 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15556652 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/556652
FPGA Clock Signal Self-detection Method Jan 3, 2016 Abandoned
Array ( [id] => 14618195 [patent_doc_number] => 10361810 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-23 [patent_title] => Data packet transmission/reception apparatus and method [patent_app_type] => utility [patent_app_number] => 14/981042 [patent_app_country] => US [patent_app_date] => 2015-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8439 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 359 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14981042 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/981042
Data packet transmission/reception apparatus and method Dec 27, 2015 Issued
Array ( [id] => 13226651 [patent_doc_number] => 10127101 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-13 [patent_title] => Memory device error check and scrub mode and error transparency [patent_app_type] => utility [patent_app_number] => 14/998184 [patent_app_country] => US [patent_app_date] => 2015-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 13953 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14998184 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/998184
Memory device error check and scrub mode and error transparency Dec 25, 2015 Issued
Array ( [id] => 13256755 [patent_doc_number] => 10141071 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-27 [patent_title] => Predictive count fail byte (CFBYTE) for non-volatile memory [patent_app_type] => utility [patent_app_number] => 14/998119 [patent_app_country] => US [patent_app_date] => 2015-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 8099 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14998119 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/998119
Predictive count fail byte (CFBYTE) for non-volatile memory Dec 25, 2015 Issued
Array ( [id] => 11716974 [patent_doc_number] => 20170185473 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-29 [patent_title] => 'Method and apparatus for partial cache line sparing' [patent_app_type] => utility [patent_app_number] => 14/757905 [patent_app_country] => US [patent_app_date] => 2015-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5949 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14757905 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/757905
Method and apparatus for partial cache line sparing Dec 22, 2015 Issued
Array ( [id] => 13003991 [patent_doc_number] => 10025664 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-17 [patent_title] => Selective buffer protection [patent_app_type] => utility [patent_app_number] => 14/979278 [patent_app_country] => US [patent_app_date] => 2015-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 8267 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14979278 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/979278
Selective buffer protection Dec 21, 2015 Issued
Array ( [id] => 11028509 [patent_doc_number] => 20160225465 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-04 [patent_title] => 'MEMORY TESTING CIRCUIT AND TESTING METHOD USING SAME' [patent_app_type] => utility [patent_app_number] => 14/978885 [patent_app_country] => US [patent_app_date] => 2015-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2823 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14978885 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/978885
Memory testing circuit and testing method using same Dec 21, 2015 Issued
Array ( [id] => 10982653 [patent_doc_number] => 20160179597 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-23 [patent_title] => 'FAILED BIT COUNT MEMORY ANALYTICS' [patent_app_type] => utility [patent_app_number] => 14/977144 [patent_app_country] => US [patent_app_date] => 2015-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 19894 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14977144 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/977144
Failed bit count memory analytics Dec 20, 2015 Issued
Array ( [id] => 11708760 [patent_doc_number] => 20170177259 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-22 [patent_title] => 'Techniques to Use Open Bit Line Information for a Memory System' [patent_app_type] => utility [patent_app_number] => 14/975543 [patent_app_country] => US [patent_app_date] => 2015-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11282 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14975543 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/975543
Techniques to Use Open Bit Line Information for a Memory System Dec 17, 2015 Abandoned
Array ( [id] => 11708036 [patent_doc_number] => 20170176535 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-22 [patent_title] => 'CLOCK GATING FOR X-BOUNDING TIMING EXCEPTIONS IN IC TESTING' [patent_app_type] => utility [patent_app_number] => 14/973624 [patent_app_country] => US [patent_app_date] => 2015-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5792 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14973624 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/973624
Clock gating for X-bounding timing exceptions in IC testing Dec 16, 2015 Issued
Array ( [id] => 12952672 [patent_doc_number] => 09837027 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-12-05 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 14/972660 [patent_app_country] => US [patent_app_date] => 2015-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6406 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14972660 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/972660
Semiconductor device Dec 16, 2015 Issued
Array ( [id] => 11708936 [patent_doc_number] => 20170177435 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-22 [patent_title] => 'Sharing Memory Between Processors in a Wireless Sensor Device' [patent_app_type] => utility [patent_app_number] => 14/971162 [patent_app_country] => US [patent_app_date] => 2015-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4956 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14971162 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/971162
Sharing Memory Between Processors in a Wireless Sensor Device Dec 15, 2015 Abandoned
Array ( [id] => 10809355 [patent_doc_number] => 20160155514 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-02 [patent_title] => 'SYSTEM AND METHOD OF TESTING AND IDENTIFYING MEMORY DEVICES' [patent_app_type] => utility [patent_app_number] => 14/955144 [patent_app_country] => US [patent_app_date] => 2015-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8766 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14955144 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/955144
SYSTEM AND METHOD OF TESTING AND IDENTIFYING MEMORY DEVICES Nov 30, 2015 Abandoned
Array ( [id] => 12948745 [patent_doc_number] => 09835685 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-12-05 [patent_title] => Test circuit and method for controlling test circuit [patent_app_type] => utility [patent_app_number] => 14/954257 [patent_app_country] => US [patent_app_date] => 2015-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 18010 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14954257 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/954257
Test circuit and method for controlling test circuit Nov 29, 2015 Issued
Menu