Search

Ana J. Picon-feliciano

Examiner (ID: 3342, Phone: (571)272-5252 , Office: P/2482 )

Most Active Art Unit
2482
Art Unit(s)
2482
Total Applications
463
Issued Applications
290
Pending Applications
56
Abandoned Applications
137

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12955969 [patent_doc_number] => 09838159 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-12-05 [patent_title] => Correction of demodulation errors based on machine learning [patent_app_type] => utility [patent_app_number] => 14/953931 [patent_app_country] => US [patent_app_date] => 2015-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 20 [patent_no_of_words] => 9596 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14953931 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/953931
Correction of demodulation errors based on machine learning Nov 29, 2015 Issued
Array ( [id] => 13113037 [patent_doc_number] => 10075187 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-09-11 [patent_title] => MCS/PMI/RI selection and coding/interleaving mechanism for bursty interference and puncturing handling [patent_app_type] => utility [patent_app_number] => 14/942265 [patent_app_country] => US [patent_app_date] => 2015-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 13405 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14942265 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/942265
MCS/PMI/RI selection and coding/interleaving mechanism for bursty interference and puncturing handling Nov 15, 2015 Issued
Array ( [id] => 11631689 [patent_doc_number] => 20170141878 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-18 [patent_title] => 'SYSTEMS AND METHODS FOR SENDING DATA FROM NON-VOLATILE SOLID STATE DEVICES BEFORE ERROR CORRECTION' [patent_app_type] => utility [patent_app_number] => 14/942516 [patent_app_country] => US [patent_app_date] => 2015-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3641 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14942516 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/942516
SYSTEMS AND METHODS FOR SENDING DATA FROM NON-VOLATILE SOLID STATE DEVICES BEFORE ERROR CORRECTION Nov 15, 2015 Abandoned
Array ( [id] => 10777888 [patent_doc_number] => 20160124044 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-05 [patent_title] => 'FAILURE DIAGNOSIS SYSTEM, FAILURE DIAGNOSIS METHOD, AND FAILURE DIAGNOSIS PROGRAM' [patent_app_type] => utility [patent_app_number] => 14/927247 [patent_app_country] => US [patent_app_date] => 2015-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8563 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14927247 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/927247
FAILURE DIAGNOSIS SYSTEM, FAILURE DIAGNOSIS METHOD, AND FAILURE DIAGNOSIS PROGRAM Oct 28, 2015 Abandoned
Array ( [id] => 11930959 [patent_doc_number] => 09797949 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-24 [patent_title] => 'Test circuit and method of controlling test circuit' [patent_app_type] => utility [patent_app_number] => 14/919105 [patent_app_country] => US [patent_app_date] => 2015-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 18 [patent_no_of_words] => 38310 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14919105 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/919105
Test circuit and method of controlling test circuit Oct 20, 2015 Issued
Array ( [id] => 11764979 [patent_doc_number] => 09373420 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-06-21 [patent_title] => 'Semiconductor test device' [patent_app_type] => utility [patent_app_number] => 14/918361 [patent_app_country] => US [patent_app_date] => 2015-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5459 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14918361 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/918361
Semiconductor test device Oct 19, 2015 Issued
Array ( [id] => 10689291 [patent_doc_number] => 20160035436 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-04 [patent_title] => 'APPARATUSES AND METHODS FOR OPERATING A MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 14/880504 [patent_app_country] => US [patent_app_date] => 2015-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5904 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14880504 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/880504
Apparatuses and methods for operating a memory device Oct 11, 2015 Issued
Array ( [id] => 11911020 [patent_doc_number] => 09779838 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-03 [patent_title] => 'Method of improving error checking and correction performance of memory' [patent_app_type] => utility [patent_app_number] => 14/839223 [patent_app_country] => US [patent_app_date] => 2015-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 7715 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14839223 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/839223
Method of improving error checking and correction performance of memory Aug 27, 2015 Issued
Array ( [id] => 11845754 [patent_doc_number] => 09733305 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-15 [patent_title] => 'Frequency-domain high-speed bus signal integrity compliance model' [patent_app_type] => utility [patent_app_number] => 14/833409 [patent_app_country] => US [patent_app_date] => 2015-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6177 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14833409 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/833409
Frequency-domain high-speed bus signal integrity compliance model Aug 23, 2015 Issued
Array ( [id] => 11316363 [patent_doc_number] => 20160352473 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-01 [patent_title] => 'FREQUENCY-DOMAIN HIGH-SPEED BUS SIGNAL INTEGRITY COMPLIANCE MODEL' [patent_app_type] => utility [patent_app_number] => 14/833643 [patent_app_country] => US [patent_app_date] => 2015-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6185 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14833643 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/833643
Frequency-domain high-speed bus signal integrity compliance model Aug 23, 2015 Issued
Array ( [id] => 10470262 [patent_doc_number] => 20150355278 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-10 [patent_title] => 'SCAN-BASED MCM INTERCONNECT TESTING' [patent_app_type] => utility [patent_app_number] => 14/830899 [patent_app_country] => US [patent_app_date] => 2015-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4187 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14830899 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/830899
Scan-based MCM interconnect testing Aug 19, 2015 Issued
Array ( [id] => 10734304 [patent_doc_number] => 20160080454 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-17 [patent_title] => 'TELECOMMUNICATION NETWORK MANAGER' [patent_app_type] => utility [patent_app_number] => 14/831783 [patent_app_country] => US [patent_app_date] => 2015-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 8999 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14831783 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/831783
Telecommunication network manager Aug 19, 2015 Issued
Array ( [id] => 11430236 [patent_doc_number] => 09568549 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-02-14 [patent_title] => 'Managing redundancy repair using boundary scans' [patent_app_type] => utility [patent_app_number] => 14/823338 [patent_app_country] => US [patent_app_date] => 2015-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 16744 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14823338 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/823338
Managing redundancy repair using boundary scans Aug 10, 2015 Issued
Array ( [id] => 10708240 [patent_doc_number] => 20160054387 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-25 [patent_title] => 'METHOD FOR PROVIDING AN ON-CHIP VARIATION DETERMINATION AND INTEGRATED CIRCUIT UTILIZING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/812219 [patent_app_country] => US [patent_app_date] => 2015-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5205 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14812219 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/812219
Method for providing an on-chip variation determination and integrated circuit utilizing the same Jul 28, 2015 Issued
Array ( [id] => 14802541 [patent_doc_number] => 10404284 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-09-03 [patent_title] => Parallel-to-parallel conversion and reordering of a block of data elements [patent_app_type] => utility [patent_app_number] => 14/805155 [patent_app_country] => US [patent_app_date] => 2015-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 18 [patent_no_of_words] => 10202 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14805155 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/805155
Parallel-to-parallel conversion and reordering of a block of data elements Jul 20, 2015 Issued
Array ( [id] => 12166986 [patent_doc_number] => 09885754 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-06 [patent_title] => 'Integrated circuit with self-verification function, verification method and method for generating a BIST signature adjustment code' [patent_app_type] => utility [patent_app_number] => 14/753032 [patent_app_country] => US [patent_app_date] => 2015-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3112 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14753032 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/753032
Integrated circuit with self-verification function, verification method and method for generating a BIST signature adjustment code Jun 28, 2015 Issued
Array ( [id] => 10770376 [patent_doc_number] => 20160116532 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-28 [patent_title] => 'TEST METHOD AND TEST APPARATUS FOR TESTING A PLURALITY OF BLOCKS IN A CIRCUIT' [patent_app_type] => utility [patent_app_number] => 14/746973 [patent_app_country] => US [patent_app_date] => 2015-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8772 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14746973 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/746973
Test method and test apparatus for testing a plurality of blocks in a circuit Jun 22, 2015 Issued
Array ( [id] => 10981752 [patent_doc_number] => 20160178695 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-23 [patent_title] => 'TEST CIRCUIT FOR VERY LOW VOLTAGE AND BIAS SCAN TESTING OF INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 14/743977 [patent_app_country] => US [patent_app_date] => 2015-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3882 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14743977 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/743977
Test circuit for very low voltage and bias scan testing of integrated circuit Jun 17, 2015 Issued
Array ( [id] => 11313208 [patent_doc_number] => 20160349319 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-01 [patent_title] => 'FREQUENCY-DOMAIN HIGH-SPEED BUS SIGNAL INTEGRITY COMPLIANCE MODEL' [patent_app_type] => utility [patent_app_number] => 14/721788 [patent_app_country] => US [patent_app_date] => 2015-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6333 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14721788 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/721788
Frequency-domain high-speed bus signal integrity compliance model May 25, 2015 Issued
Array ( [id] => 11660922 [patent_doc_number] => 09673941 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-06-06 [patent_title] => 'Frequency-domain high-speed bus signal integrity compliance model' [patent_app_type] => utility [patent_app_number] => 14/721862 [patent_app_country] => US [patent_app_date] => 2015-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6271 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14721862 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/721862
Frequency-domain high-speed bus signal integrity compliance model May 25, 2015 Issued
Menu