
Ana J. Picon-feliciano
Examiner (ID: 3342, Phone: (571)272-5252 , Office: P/2482 )
| Most Active Art Unit | 2482 |
| Art Unit(s) | 2482 |
| Total Applications | 463 |
| Issued Applications | 290 |
| Pending Applications | 56 |
| Abandoned Applications | 137 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
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[id] => 11035098
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[patent_kind] => A1
[patent_issue_date] => 2016-08-11
[patent_title] => 'MEMORY MANAGEMENT METHOD, MEMORY CONTROL CIRCUIT UNIT AND MEMORY STORAGE APPARATUS'
[patent_app_type] => utility
[patent_app_number] => 14/693885
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Array
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[patent_kind] => B2
[patent_issue_date] => 2018-04-03
[patent_title] => Verification of storage media upon deployment
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Array
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[patent_issue_date] => 2017-07-18
[patent_title] => 'Method and apparatus for optimized memory test status detection and debug'
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[patent_app_date] => 2015-04-01
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Array
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[patent_doc_number] => 09548136
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[patent_kind] => B2
[patent_issue_date] => 2017-01-17
[patent_title] => 'Method to identify extrinsic SRAM bits for failure analysis based on fail count voltage response'
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Array
(
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[patent_doc_number] => 20180240532
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[patent_title] => MEMORY DIAGNOSIS APPARATUS AND MEMORY DIAGNOSIS PROGRAM
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/554751 | Memory diagnosis apparatus and memory diagnosis program | Mar 9, 2015 | Issued |
Array
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[patent_issue_date] => 2015-08-27
[patent_title] => 'BIT INTERLEAVER AND BIT DE-INTERLEAVER'
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/627856 | Integrated circuit (IC) with primary and secondary networks and device containing such an IC | Feb 19, 2015 | Issued |
Array
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[patent_title] => 'Techniques for using scan storage circuits'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/610341 | Techniques for using scan storage circuits | Jan 29, 2015 | Issued |
Array
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[id] => 11918166
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[patent_title] => 'Memory device with adaptive voltage scaling based on error information'
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Array
(
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[patent_doc_number] => 20160061892
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[patent_issue_date] => 2016-03-03
[patent_title] => 'SCAN PROGRAMMABLE REGISTER CONTROLLED CLOCK ARCHITECTURE FOR TESTING ASYNCHRONOUS DOMAINS'
[patent_app_type] => utility
[patent_app_number] => 14/609341
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/609341 | SCAN PROGRAMMABLE REGISTER CONTROLLED CLOCK ARCHITECTURE FOR TESTING ASYNCHRONOUS DOMAINS | Jan 28, 2015 | Abandoned |
Array
(
[id] => 10477536
[patent_doc_number] => 20150362554
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[patent_title] => 'SYSTEM ON CHIP'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/607607 | System on chip | Jan 27, 2015 | Issued |
Array
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[patent_title] => 'Read disturb detection'
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Array
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Array
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[patent_title] => 'INSERTING BYPASS STRUCTURES AT TAP POINTS TO REDUCE LATCH DEPENDENCY DURING SCAN TESTING'
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Array
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[patent_title] => 'MONITORING SERIAL LINK ERRORS'
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Array
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