Search

Ana J. Picon-feliciano

Examiner (ID: 3342, Phone: (571)272-5252 , Office: P/2482 )

Most Active Art Unit
2482
Art Unit(s)
2482
Total Applications
463
Issued Applications
290
Pending Applications
56
Abandoned Applications
137

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11035098 [patent_doc_number] => 20160232053 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-11 [patent_title] => 'MEMORY MANAGEMENT METHOD, MEMORY CONTROL CIRCUIT UNIT AND MEMORY STORAGE APPARATUS' [patent_app_type] => utility [patent_app_number] => 14/693885 [patent_app_country] => US [patent_app_date] => 2015-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 12462 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14693885 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/693885
Memory management method, memory control circuit unit and memory storage apparatus Apr 22, 2015 Issued
Array ( [id] => 12293556 [patent_doc_number] => 09934871 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-03 [patent_title] => Verification of storage media upon deployment [patent_app_type] => utility [patent_app_number] => 14/689770 [patent_app_country] => US [patent_app_date] => 2015-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4863 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14689770 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/689770
Verification of storage media upon deployment Apr 16, 2015 Issued
Array ( [id] => 11753223 [patent_doc_number] => 09711241 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-07-18 [patent_title] => 'Method and apparatus for optimized memory test status detection and debug' [patent_app_type] => utility [patent_app_number] => 14/676501 [patent_app_country] => US [patent_app_date] => 2015-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3480 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14676501 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/676501
Method and apparatus for optimized memory test status detection and debug Mar 31, 2015 Issued
Array ( [id] => 11807053 [patent_doc_number] => 09548136 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-17 [patent_title] => 'Method to identify extrinsic SRAM bits for failure analysis based on fail count voltage response' [patent_app_type] => utility [patent_app_number] => 14/664959 [patent_app_country] => US [patent_app_date] => 2015-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2552 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14664959 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/664959
Method to identify extrinsic SRAM bits for failure analysis based on fail count voltage response Mar 22, 2015 Issued
Array ( [id] => 13377981 [patent_doc_number] => 20180240532 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-23 [patent_title] => MEMORY DIAGNOSIS APPARATUS AND MEMORY DIAGNOSIS PROGRAM [patent_app_type] => utility [patent_app_number] => 15/554751 [patent_app_country] => US [patent_app_date] => 2015-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3831 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15554751 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/554751
Memory diagnosis apparatus and memory diagnosis program Mar 9, 2015 Issued
Array ( [id] => 10359393 [patent_doc_number] => 20150244398 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-27 [patent_title] => 'BIT INTERLEAVER AND BIT DE-INTERLEAVER' [patent_app_type] => utility [patent_app_number] => 14/628456 [patent_app_country] => US [patent_app_date] => 2015-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7231 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14628456 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/628456
Bit interleaver and bit de-interleaver Feb 22, 2015 Issued
Array ( [id] => 11522783 [patent_doc_number] => 09606176 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-28 [patent_title] => 'Integrated circuit (IC) with primary and secondary networks and device containing such an IC' [patent_app_type] => utility [patent_app_number] => 14/627856 [patent_app_country] => US [patent_app_date] => 2015-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 73 [patent_figures_cnt] => 75 [patent_no_of_words] => 56177 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14627856 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/627856
Integrated circuit (IC) with primary and secondary networks and device containing such an IC Feb 19, 2015 Issued
Array ( [id] => 11481638 [patent_doc_number] => 09588176 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-03-07 [patent_title] => 'Techniques for using scan storage circuits' [patent_app_type] => utility [patent_app_number] => 14/610341 [patent_app_country] => US [patent_app_date] => 2015-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6895 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14610341 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/610341
Techniques for using scan storage circuits Jan 29, 2015 Issued
Array ( [id] => 11918166 [patent_doc_number] => 09786356 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-10 [patent_title] => 'Memory device with adaptive voltage scaling based on error information' [patent_app_type] => utility [patent_app_number] => 14/611056 [patent_app_country] => US [patent_app_date] => 2015-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 14643 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14611056 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/611056
Memory device with adaptive voltage scaling based on error information Jan 29, 2015 Issued
Array ( [id] => 10715745 [patent_doc_number] => 20160061892 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-03 [patent_title] => 'SCAN PROGRAMMABLE REGISTER CONTROLLED CLOCK ARCHITECTURE FOR TESTING ASYNCHRONOUS DOMAINS' [patent_app_type] => utility [patent_app_number] => 14/609341 [patent_app_country] => US [patent_app_date] => 2015-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3926 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14609341 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/609341
SCAN PROGRAMMABLE REGISTER CONTROLLED CLOCK ARCHITECTURE FOR TESTING ASYNCHRONOUS DOMAINS Jan 28, 2015 Abandoned
Array ( [id] => 10477536 [patent_doc_number] => 20150362554 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-17 [patent_title] => 'SYSTEM ON CHIP' [patent_app_type] => utility [patent_app_number] => 14/607607 [patent_app_country] => US [patent_app_date] => 2015-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7565 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14607607 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/607607
System on chip Jan 27, 2015 Issued
Array ( [id] => 11431876 [patent_doc_number] => 09570198 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-02-14 [patent_title] => 'Read disturb detection' [patent_app_type] => utility [patent_app_number] => 14/602151 [patent_app_country] => US [patent_app_date] => 2015-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5266 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14602151 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/602151
Read disturb detection Jan 20, 2015 Issued
Array ( [id] => 11615324 [patent_doc_number] => 09653186 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-05-16 [patent_title] => 'Memory-testing device and memory-testing method' [patent_app_type] => utility [patent_app_number] => 14/600496 [patent_app_country] => US [patent_app_date] => 2015-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 4260 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14600496 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/600496
Memory-testing device and memory-testing method Jan 19, 2015 Issued
Array ( [id] => 10823807 [patent_doc_number] => 20160169972 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-16 [patent_title] => 'INSERTING BYPASS STRUCTURES AT TAP POINTS TO REDUCE LATCH DEPENDENCY DURING SCAN TESTING' [patent_app_type] => utility [patent_app_number] => 14/574613 [patent_app_country] => US [patent_app_date] => 2014-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4155 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14574613 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/574613
Inserting bypass structures at tap points to reduce latch dependency during scan testing Dec 17, 2014 Issued
Array ( [id] => 10982652 [patent_doc_number] => 20160179595 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-23 [patent_title] => 'MONITORING SERIAL LINK ERRORS' [patent_app_type] => utility [patent_app_number] => 14/575590 [patent_app_country] => US [patent_app_date] => 2014-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6395 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14575590 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/575590
Monitoring serial link errors Dec 17, 2014 Issued
Array ( [id] => 11390508 [patent_doc_number] => 09551747 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-24 [patent_title] => 'Inserting bypass structures at tap points to reduce latch dependency during scan testing' [patent_app_type] => utility [patent_app_number] => 14/568312 [patent_app_country] => US [patent_app_date] => 2014-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4109 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14568312 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/568312
Inserting bypass structures at tap points to reduce latch dependency during scan testing Dec 11, 2014 Issued
Array ( [id] => 11508520 [patent_doc_number] => 09599672 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-21 [patent_title] => 'Integrated circuit with scan chain having dual-edge triggered scannable flip flops and method of operating thereof' [patent_app_type] => utility [patent_app_number] => 14/566833 [patent_app_country] => US [patent_app_date] => 2014-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 8492 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14566833 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/566833
Integrated circuit with scan chain having dual-edge triggered scannable flip flops and method of operating thereof Dec 10, 2014 Issued
Array ( [id] => 11525246 [patent_doc_number] => 09608666 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-03-28 [patent_title] => 'Non-concatenated FEC codes for ultra-high speed optical transport networks' [patent_app_type] => utility [patent_app_number] => 14/561183 [patent_app_country] => US [patent_app_date] => 2014-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 20 [patent_no_of_words] => 9225 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14561183 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/561183
Non-concatenated FEC codes for ultra-high speed optical transport networks Dec 3, 2014 Issued
Array ( [id] => 10802551 [patent_doc_number] => 20160148708 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-26 [patent_title] => 'Defect Logging in Nonvolatile Memory' [patent_app_type] => utility [patent_app_number] => 14/550290 [patent_app_country] => US [patent_app_date] => 2014-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 11333 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14550290 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/550290
Defect logging in nonvolatile memory Nov 20, 2014 Issued
Array ( [id] => 11080182 [patent_doc_number] => 20160277146 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-22 [patent_title] => 'METHOD AND APPARATUS FOR TRANSMITTING AND RECEIVING PACKET IN COMMUNICATION SYSTEM' [patent_app_type] => utility [patent_app_number] => 15/032002 [patent_app_country] => US [patent_app_date] => 2014-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 9921 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15032002 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/032002
Method and apparatus for transmitting and receiving packet in communication system Oct 30, 2014 Issued
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