Search

Ana J. Picon-feliciano

Examiner (ID: 3342, Phone: (571)272-5252 , Office: P/2482 )

Most Active Art Unit
2482
Art Unit(s)
2482
Total Applications
463
Issued Applications
290
Pending Applications
56
Abandoned Applications
137

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10556210 [patent_doc_number] => 09280412 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-08 [patent_title] => 'Memory with error correction configured to prevent overcorrection' [patent_app_type] => utility [patent_app_number] => 13/890698 [patent_app_country] => US [patent_app_date] => 2013-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4950 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13890698 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/890698
Memory with error correction configured to prevent overcorrection May 8, 2013 Issued
Array ( [id] => 10928076 [patent_doc_number] => 20140331097 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-11-06 [patent_title] => 'MANAGING REDUNDANCY REPAIR USING BOUNDARY SCANS' [patent_app_type] => utility [patent_app_number] => 13/887674 [patent_app_country] => US [patent_app_date] => 2013-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 15999 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13887674 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/887674
Managing redundancy repair using boundary scans May 5, 2013 Issued
Array ( [id] => 9071204 [patent_doc_number] => 20130262959 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-03 [patent_title] => 'TEMPORARILY STORING AN ENCODED DATA SLICE' [patent_app_type] => utility [patent_app_number] => 13/887662 [patent_app_country] => US [patent_app_date] => 2013-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 26580 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13887662 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/887662
Temporarily storing an encoded data slice May 5, 2013 Issued
Array ( [id] => 9017422 [patent_doc_number] => 20130232386 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-05 [patent_title] => 'MEMORY DEVICES, TESTING SYSTEMS AND METHODS' [patent_app_type] => utility [patent_app_number] => 13/867790 [patent_app_country] => US [patent_app_date] => 2013-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4784 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13867790 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/867790
Memory devices, testing systems and methods Apr 21, 2013 Issued
Array ( [id] => 9673453 [patent_doc_number] => 20140237316 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-21 [patent_title] => 'ENCODING WITH INTEGRATED ERROR-DETECTION' [patent_app_type] => utility [patent_app_number] => 13/773329 [patent_app_country] => US [patent_app_date] => 2013-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4715 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13773329 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/773329
Encoding with integrated error-detection Feb 20, 2013 Issued
Array ( [id] => 9341594 [patent_doc_number] => 20140068378 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-06 [patent_title] => 'SEMICONDUCTOR STORAGE DEVICE AND MEMORY CONTROLLER' [patent_app_type] => utility [patent_app_number] => 13/772659 [patent_app_country] => US [patent_app_date] => 2013-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10812 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13772659 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/772659
SEMICONDUCTOR STORAGE DEVICE AND MEMORY CONTROLLER Feb 20, 2013 Abandoned
Array ( [id] => 9673449 [patent_doc_number] => 20140237312 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-21 [patent_title] => 'Scan Warmup Scheme for Mitigating DI/DT During Scan Test' [patent_app_type] => utility [patent_app_number] => 13/773501 [patent_app_country] => US [patent_app_date] => 2013-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3962 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13773501 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/773501
Scan warmup scheme for mitigating di/dt during scan test Feb 20, 2013 Issued
Array ( [id] => 11418086 [patent_doc_number] => 09564920 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-02-07 [patent_title] => 'Method and apparatus for mitigation of false packet decodes due to early decoding' [patent_app_type] => utility [patent_app_number] => 13/771852 [patent_app_country] => US [patent_app_date] => 2013-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10790 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13771852 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/771852
Method and apparatus for mitigation of false packet decodes due to early decoding Feb 19, 2013 Issued
Array ( [id] => 10136983 [patent_doc_number] => 09170301 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-10-27 [patent_title] => 'Hierarchical compaction for test pattern power generation' [patent_app_type] => utility [patent_app_number] => 13/772245 [patent_app_country] => US [patent_app_date] => 2013-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 9759 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 313 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13772245 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/772245
Hierarchical compaction for test pattern power generation Feb 19, 2013 Issued
Array ( [id] => 10631334 [patent_doc_number] => 09349489 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-24 [patent_title] => 'Systems and methods to update reference voltages in response to data retention in non-volatile memory' [patent_app_type] => utility [patent_app_number] => 13/771894 [patent_app_country] => US [patent_app_date] => 2013-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7921 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13771894 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/771894
Systems and methods to update reference voltages in response to data retention in non-volatile memory Feb 19, 2013 Issued
Array ( [id] => 9673451 [patent_doc_number] => 20140237314 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-21 [patent_title] => 'Systems and Methods for Skip Layer Data Decoding' [patent_app_type] => utility [patent_app_number] => 13/770008 [patent_app_country] => US [patent_app_date] => 2013-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8927 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13770008 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/770008
Systems and methods for skip layer data decoding Feb 18, 2013 Issued
Array ( [id] => 10196440 [patent_doc_number] => 09225357 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-12-29 [patent_title] => 'Data packet transmission/reception apparatus and method' [patent_app_type] => utility [patent_app_number] => 13/770635 [patent_app_country] => US [patent_app_date] => 2013-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8590 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13770635 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/770635
Data packet transmission/reception apparatus and method Feb 18, 2013 Issued
Array ( [id] => 9673458 [patent_doc_number] => 20140237321 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-21 [patent_title] => 'SOLID STATE DRIVE CACHE RECOVERY IN A CLUSTERED STORAGE SYSTEM' [patent_app_type] => utility [patent_app_number] => 13/769858 [patent_app_country] => US [patent_app_date] => 2013-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8040 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13769858 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/769858
Solid state drive cache recovery in a clustered storage system Feb 18, 2013 Issued
Array ( [id] => 9919296 [patent_doc_number] => 20150074501 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-12 [patent_title] => 'Cascaded Viterbi Bitstream Generator' [patent_app_type] => utility [patent_app_number] => 14/380880 [patent_app_country] => US [patent_app_date] => 2013-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7715 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14380880 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/380880
Cascaded viterbi bitstream generator Jan 17, 2013 Issued
Array ( [id] => 9006242 [patent_doc_number] => 20130227367 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-29 [patent_title] => 'Test IP-Based A.T.E. Instrument Architecture' [patent_app_type] => utility [patent_app_number] => 13/742589 [patent_app_country] => US [patent_app_date] => 2013-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7671 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13742589 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/742589
Test IP-Based A.T.E. Instrument Architecture Jan 15, 2013 Abandoned
Array ( [id] => 10748160 [patent_doc_number] => 20160094311 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-31 [patent_title] => 'ETHERNET DATA PROCESSING METHOD, PHYSICAL LAYER CHIP AND ETHERNET EQUIPMENT' [patent_app_type] => utility [patent_app_number] => 14/891778 [patent_app_country] => US [patent_app_date] => 2013-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 13226 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14891778 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/891778
Ethernet data processing method, physical layer chip and Ethernet equipment Jan 3, 2013 Issued
Array ( [id] => 9571744 [patent_doc_number] => 20140189457 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-03 [patent_title] => 'INPUT/OUTPUT DELAY TESTING FOR DEVICES UTILIZING ON-CHIP DELAY GENERATION' [patent_app_type] => utility [patent_app_number] => 13/728741 [patent_app_country] => US [patent_app_date] => 2012-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 10041 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13728741 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/728741
Input/output delay testing for devices utilizing on-chip delay generation Dec 26, 2012 Issued
Array ( [id] => 9563908 [patent_doc_number] => 20140181621 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-26 [patent_title] => 'METHOD OF ARRANGING DATA IN A NON-VOLATILE MEMORY AND A MEMORY CONTROL SYSTEM THEREOF' [patent_app_type] => utility [patent_app_number] => 13/727487 [patent_app_country] => US [patent_app_date] => 2012-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2335 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13727487 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/727487
METHOD OF ARRANGING DATA IN A NON-VOLATILE MEMORY AND A MEMORY CONTROL SYSTEM THEREOF Dec 25, 2012 Abandoned
Array ( [id] => 9563905 [patent_doc_number] => 20140181618 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-26 [patent_title] => 'ERROR DETECTION AND CORRECTION APPARATUS AND METHOD' [patent_app_type] => utility [patent_app_number] => 13/727561 [patent_app_country] => US [patent_app_date] => 2012-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7566 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13727561 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/727561
Error detection and correction apparatus and method Dec 25, 2012 Issued
Array ( [id] => 10873318 [patent_doc_number] => 08898539 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-11-25 [patent_title] => 'Correcting errors in miscorrected codewords using list decoding' [patent_app_type] => utility [patent_app_number] => 13/611158 [patent_app_country] => US [patent_app_date] => 2012-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3951 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13611158 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/611158
Correcting errors in miscorrected codewords using list decoding Sep 11, 2012 Issued
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