Search

Ana J. Picon-feliciano

Examiner (ID: 3342, Phone: (571)272-5252 , Office: P/2482 )

Most Active Art Unit
2482
Art Unit(s)
2482
Total Applications
463
Issued Applications
290
Pending Applications
56
Abandoned Applications
137

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10027793 [patent_doc_number] => 09069694 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-06-30 [patent_title] => 'Memory device and method of operating the same' [patent_app_type] => utility [patent_app_number] => 13/610996 [patent_app_country] => US [patent_app_date] => 2012-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 10297 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 9 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13610996 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/610996
Memory device and method of operating the same Sep 11, 2012 Issued
Array ( [id] => 8952806 [patent_doc_number] => 20130198587 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-01 [patent_title] => 'MEMORY BUFFER PERFORMING ERROR CORRECTION CODING (ECC)' [patent_app_type] => utility [patent_app_number] => 13/611566 [patent_app_country] => US [patent_app_date] => 2012-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6190 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13611566 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/611566
MEMORY BUFFER PERFORMING ERROR CORRECTION CODING (ECC) Sep 11, 2012 Abandoned
Array ( [id] => 8794335 [patent_doc_number] => 20130111304 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-02 [patent_title] => 'CYCLIC CODE DECODING METHOD AND CYCLIC CODE DECODER' [patent_app_type] => utility [patent_app_number] => 13/609829 [patent_app_country] => US [patent_app_date] => 2012-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4150 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13609829 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/609829
Cyclic code decoding method and cyclic code decoder Sep 10, 2012 Issued
Array ( [id] => 8746732 [patent_doc_number] => 20130086449 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-04 [patent_title] => 'Sharing a Check Bit Memory Device Between Groups of Memory Devices' [patent_app_type] => utility [patent_app_number] => 13/610675 [patent_app_country] => US [patent_app_date] => 2012-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7767 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13610675 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/610675
Sharing a check bit memory device between groups of memory devices Sep 10, 2012 Issued
Array ( [id] => 9365388 [patent_doc_number] => 20140075261 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-13 [patent_title] => 'OPTIMIZED MECHANISM TO SIMPLIFY THE CIRCULANT SHIFTER AND THE P/Q KICK OUT FOR LAYERED LDPC DECODER' [patent_app_type] => utility [patent_app_number] => 13/607907 [patent_app_country] => US [patent_app_date] => 2012-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2613 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13607907 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/607907
Optimized mechanism to simplify the circulant shifter and the P/Q kick out for layered LDPC decoder Sep 9, 2012 Issued
Array ( [id] => 9853084 [patent_doc_number] => 08954832 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-02-10 [patent_title] => 'Asymmetric distance coding' [patent_app_type] => utility [patent_app_number] => 13/603843 [patent_app_country] => US [patent_app_date] => 2012-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 12694 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13603843 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/603843
Asymmetric distance coding Sep 4, 2012 Issued
Array ( [id] => 9276066 [patent_doc_number] => 08640013 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-01-28 [patent_title] => 'Storage device' [patent_app_type] => utility [patent_app_number] => 13/601707 [patent_app_country] => US [patent_app_date] => 2012-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 45 [patent_no_of_words] => 22238 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13601707 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/601707
Storage device Aug 30, 2012 Issued
Array ( [id] => 8906482 [patent_doc_number] => 20130173985 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-07-04 [patent_title] => 'METHOD OF READING DATA FROM STORAGE DEVICE, ERROR CORRECTION DEVICE AND STORAGE SYSTEM INCLUDING ERROR CORRECTION CODE DECODER' [patent_app_type] => utility [patent_app_number] => 13/601057 [patent_app_country] => US [patent_app_date] => 2012-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 14355 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13601057 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/601057
Method of reading data from storage device, error correction device and storage system including error correction code decoder Aug 30, 2012 Issued
Array ( [id] => 8699104 [patent_doc_number] => 20130061113 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-03-07 [patent_title] => 'METHOD OF CORRECTING ERRORS AND MEMORY DEVICE USING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/599467 [patent_app_country] => US [patent_app_date] => 2012-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7532 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13599467 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/599467
METHOD OF CORRECTING ERRORS AND MEMORY DEVICE USING THE SAME Aug 29, 2012 Abandoned
Array ( [id] => 8906480 [patent_doc_number] => 20130173983 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-07-04 [patent_title] => 'GENERATION OF PROGRAM DATA FOR NONVOLATILE MEMORY' [patent_app_type] => utility [patent_app_number] => 13/598978 [patent_app_country] => US [patent_app_date] => 2012-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 7852 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13598978 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/598978
Generation of program data for nonvolatile memory Aug 29, 2012 Issued
Array ( [id] => 11253771 [patent_doc_number] => 09479290 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-10-25 [patent_title] => 'Method and apparatus for transmitting and receiving information in a broadcasting/communication system' [patent_app_type] => utility [patent_app_number] => 13/599551 [patent_app_country] => US [patent_app_date] => 2012-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 8365 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13599551 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/599551
Method and apparatus for transmitting and receiving information in a broadcasting/communication system Aug 29, 2012 Issued
Array ( [id] => 11219953 [patent_doc_number] => 09448283 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-20 [patent_title] => 'Circuit arrangement for logic built-in self-test of a semiconductor device and a method of operating such circuit arrangement' [patent_app_type] => utility [patent_app_number] => 14/421889 [patent_app_country] => US [patent_app_date] => 2012-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 6925 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 371 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14421889 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/421889
Circuit arrangement for logic built-in self-test of a semiconductor device and a method of operating such circuit arrangement Aug 21, 2012 Issued
Array ( [id] => 9102777 [patent_doc_number] => 08566671 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-10-22 [patent_title] => 'Configurable accelerated post-write read to manage errors' [patent_app_type] => utility [patent_app_number] => 13/538927 [patent_app_country] => US [patent_app_date] => 2012-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 42 [patent_no_of_words] => 20759 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 299 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13538927 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/538927
Configurable accelerated post-write read to manage errors Jun 28, 2012 Issued
Array ( [id] => 9479467 [patent_doc_number] => 20140136931 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-15 [patent_title] => 'ERROR-CORRECTING DECODER' [patent_app_type] => utility [patent_app_number] => 14/129220 [patent_app_country] => US [patent_app_date] => 2012-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4346 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14129220 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/129220
ERROR-CORRECTING DECODER Jun 25, 2012 Abandoned
Array ( [id] => 10977073 [patent_doc_number] => 20140380108 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-12-25 [patent_title] => 'METHOD AND SYSTEM TO OBTAIN STATE CONFIDENCE DATA USING MULTISTROBE READ OF A NON-VOLATILE MEMORY' [patent_app_type] => utility [patent_app_number] => 13/977011 [patent_app_country] => US [patent_app_date] => 2012-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 12845 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13977011 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/977011
Method and system to obtain state confidence data using multistrobe read of a non-volatile memory Mar 28, 2012 Issued
Array ( [id] => 8280079 [patent_doc_number] => 20120173941 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-05 [patent_title] => 'METHOD, SYSTEM AND PROCESSOR FOR LOADING LOGICAL DEVICES ONLINE' [patent_app_type] => utility [patent_app_number] => 13/416808 [patent_app_country] => US [patent_app_date] => 2012-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6785 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13416808 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/416808
METHOD, SYSTEM AND PROCESSOR FOR LOADING LOGICAL DEVICES ONLINE Mar 8, 2012 Abandoned
Array ( [id] => 8383331 [patent_doc_number] => 20120226955 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-09-06 [patent_title] => 'METHOD AND APPARATUS FOR FORWARD ERROR CORRECTION (FEC) IN A RESOURCE-CONSTRAINED NETWORK' [patent_app_type] => utility [patent_app_number] => 13/408440 [patent_app_country] => US [patent_app_date] => 2012-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8508 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13408440 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/408440
METHOD AND APPARATUS FOR FORWARD ERROR CORRECTION (FEC) IN A RESOURCE-CONSTRAINED NETWORK Feb 28, 2012 Abandoned
Array ( [id] => 8383335 [patent_doc_number] => 20120226966 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-09-06 [patent_title] => 'System and Method for Device Identification in a Communications System' [patent_app_type] => utility [patent_app_number] => 13/407953 [patent_app_country] => US [patent_app_date] => 2012-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 11308 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13407953 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/407953
System and Method for Device Identification in a Communications System Feb 28, 2012 Abandoned
Array ( [id] => 10106540 [patent_doc_number] => 09142323 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-09-22 [patent_title] => 'Hardware acceleration of DSP error recovery for flash memory' [patent_app_type] => utility [patent_app_number] => 13/408913 [patent_app_country] => US [patent_app_date] => 2012-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4250 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13408913 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/408913
Hardware acceleration of DSP error recovery for flash memory Feb 28, 2012 Issued
Array ( [id] => 8372519 [patent_doc_number] => 20120221906 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-30 [patent_title] => 'SCAN-BASED MCM INTERCONNECTING TESTING' [patent_app_type] => utility [patent_app_number] => 13/407369 [patent_app_country] => US [patent_app_date] => 2012-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4160 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13407369 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/407369
Scan-based MCM interconnecting testing Feb 27, 2012 Issued
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