Search

Ana J. Picon-feliciano

Examiner (ID: 3342, Phone: (571)272-5252 , Office: P/2482 )

Most Active Art Unit
2482
Art Unit(s)
2482
Total Applications
463
Issued Applications
290
Pending Applications
56
Abandoned Applications
137

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7809102 [patent_doc_number] => 20120060056 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-08 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/225621 [patent_app_country] => US [patent_app_date] => 2011-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3548 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0060/20120060056.pdf [firstpage_image] =>[orig_patent_app_number] => 13225621 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/225621
Semiconductor memory device and method of operating the same Sep 5, 2011 Issued
Array ( [id] => 7658483 [patent_doc_number] => 20110307752 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-15 [patent_title] => 'SEMICONDUCTOR DEVICE, AND DESIGN METHOD, DESIGN TOOL, AND FAULT DETECTION METHOD OF SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/218207 [patent_app_country] => US [patent_app_date] => 2011-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 6431 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0307/20110307752.pdf [firstpage_image] =>[orig_patent_app_number] => 13218207 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/218207
SEMICONDUCTOR DEVICE, AND DESIGN METHOD, DESIGN TOOL, AND FAULT DETECTION METHOD OF SEMICONDUCTOR DEVICE Aug 24, 2011 Abandoned
Array ( [id] => 9967930 [patent_doc_number] => 09015565 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-04-21 [patent_title] => 'Method for recovery of lost data and for correction of corrupted data' [patent_app_type] => utility [patent_app_number] => 13/767979 [patent_app_country] => US [patent_app_date] => 2011-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4757 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13767979 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/767979
Method for recovery of lost data and for correction of corrupted data Aug 18, 2011 Issued
Array ( [id] => 8878813 [patent_doc_number] => 08473797 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-25 [patent_title] => 'Circuits and methods for clock malfunction detection' [patent_app_type] => utility [patent_app_number] => 13/209157 [patent_app_country] => US [patent_app_date] => 2011-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 8069 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13209157 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/209157
Circuits and methods for clock malfunction detection Aug 11, 2011 Issued
Array ( [id] => 10123998 [patent_doc_number] => 09158356 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-10-13 [patent_title] => 'Adaptive voltage scaling based on the results of forward error correction processing' [patent_app_type] => utility [patent_app_number] => 13/170747 [patent_app_country] => US [patent_app_date] => 2011-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4664 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13170747 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/170747
Adaptive voltage scaling based on the results of forward error correction processing Jun 27, 2011 Issued
Array ( [id] => 7658489 [patent_doc_number] => 20110307758 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-15 [patent_title] => 'APPARATUS, SYSTEM, AND METHOD FOR PROVIDING ERROR CORRECTION' [patent_app_type] => utility [patent_app_number] => 13/161211 [patent_app_country] => US [patent_app_date] => 2011-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 32901 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0307/20110307758.pdf [firstpage_image] =>[orig_patent_app_number] => 13161211 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/161211
APPARATUS, SYSTEM, AND METHOD FOR PROVIDING ERROR CORRECTION Jun 14, 2011 Abandoned
Array ( [id] => 7665085 [patent_doc_number] => 20110314354 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-22 [patent_title] => 'APPARATUS, SYSTEM, AND METHOD FOR PROVIDING ERROR CORRECTION' [patent_app_type] => utility [patent_app_number] => 13/160755 [patent_app_country] => US [patent_app_date] => 2011-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 32722 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13160755 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/160755
Apparatus, system, and method for providing error correction Jun 14, 2011 Issued
Array ( [id] => 8524904 [patent_doc_number] => 20120324312 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-20 [patent_title] => 'SELECTIVE MASKING FOR ERROR CORRECTION' [patent_app_type] => utility [patent_app_number] => 13/159878 [patent_app_country] => US [patent_app_date] => 2011-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5548 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13159878 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/159878
Selective masking for error correction Jun 13, 2011 Issued
Array ( [id] => 7658479 [patent_doc_number] => 20110307748 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-15 [patent_title] => 'TECHNIQUES FOR ERROR DIAGNOSIS IN VLSI SYSTEMS' [patent_app_type] => utility [patent_app_number] => 13/160423 [patent_app_country] => US [patent_app_date] => 2011-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 10721 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0307/20110307748.pdf [firstpage_image] =>[orig_patent_app_number] => 13160423 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/160423
TECHNIQUES FOR ERROR DIAGNOSIS IN VLSI SYSTEMS Jun 13, 2011 Abandoned
Array ( [id] => 9451787 [patent_doc_number] => 20140122957 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-01 [patent_title] => 'Method, an Apparatus and a Network Element for Dynamical TDD Configuration' [patent_app_type] => utility [patent_app_number] => 14/122284 [patent_app_country] => US [patent_app_date] => 2011-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4589 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14122284 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/122284
Method, an Apparatus and a Network Element for Dynamical TDD Configuration May 29, 2011 Abandoned
Array ( [id] => 8479243 [patent_doc_number] => 20120278651 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-01 [patent_title] => 'Remapping data with pointer' [patent_app_type] => utility [patent_app_number] => 13/066976 [patent_app_country] => US [patent_app_date] => 2011-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4785 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13066976 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/066976
Remapping data with pointer Apr 27, 2011 Issued
Array ( [id] => 9886052 [patent_doc_number] => 08972838 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-03 [patent_title] => 'Data transmission detecting device, data transmission detecting method and electronic device thereof' [patent_app_type] => utility [patent_app_number] => 13/089293 [patent_app_country] => US [patent_app_date] => 2011-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4390 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13089293 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/089293
Data transmission detecting device, data transmission detecting method and electronic device thereof Apr 17, 2011 Issued
Array ( [id] => 10027787 [patent_doc_number] => 09069688 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-06-30 [patent_title] => 'Dynamic optimization of back-end memory system interface' [patent_app_type] => utility [patent_app_number] => 13/087640 [patent_app_country] => US [patent_app_date] => 2011-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 25 [patent_no_of_words] => 15301 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13087640 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/087640
Dynamic optimization of back-end memory system interface Apr 14, 2011 Issued
Array ( [id] => 9954453 [patent_doc_number] => 09003266 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-04-07 [patent_title] => 'Pipelined turbo convolution code decoder' [patent_app_type] => utility [patent_app_number] => 13/088303 [patent_app_country] => US [patent_app_date] => 2011-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 6213 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13088303 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/088303
Pipelined turbo convolution code decoder Apr 14, 2011 Issued
Array ( [id] => 8455106 [patent_doc_number] => 20120266051 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-10-18 [patent_title] => 'STAIRCASE FORWARD ERROR CORRECTION CODING' [patent_app_type] => utility [patent_app_number] => 13/085810 [patent_app_country] => US [patent_app_date] => 2011-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5979 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13085810 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/085810
Staircase forward error correction coding Apr 12, 2011 Issued
Array ( [id] => 10901569 [patent_doc_number] => 08924812 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-12-30 [patent_title] => 'Non-binary LDPC code decoder' [patent_app_type] => utility [patent_app_number] => 13/082120 [patent_app_country] => US [patent_app_date] => 2011-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 14608 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13082120 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/082120
Non-binary LDPC code decoder Apr 6, 2011 Issued
Array ( [id] => 8060333 [patent_doc_number] => 20110246857 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-06 [patent_title] => 'MEMORY SYSTEM AND METHOD' [patent_app_type] => utility [patent_app_number] => 13/078364 [patent_app_country] => US [patent_app_date] => 2011-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7347 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0246/20110246857.pdf [firstpage_image] =>[orig_patent_app_number] => 13078364 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/078364
MEMORY SYSTEM AND METHOD Mar 31, 2011 Abandoned
Array ( [id] => 11431841 [patent_doc_number] => 09570162 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-02-14 [patent_title] => 'Data read method for flash memory' [patent_app_type] => utility [patent_app_number] => 13/075053 [patent_app_country] => US [patent_app_date] => 2011-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3186 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 272 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13075053 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/075053
Data read method for flash memory Mar 28, 2011 Issued
Array ( [id] => 9707419 [patent_doc_number] => 08832512 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-09 [patent_title] => 'Low power compression of incompatible test cubes' [patent_app_type] => utility [patent_app_number] => 13/049829 [patent_app_country] => US [patent_app_date] => 2011-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7983 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13049829 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/049829
Low power compression of incompatible test cubes Mar 15, 2011 Issued
Array ( [id] => 7482357 [patent_doc_number] => 20110234282 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-29 [patent_title] => 'Method And Circuit For Testing And Characterizing High Speed Signals Using An ON-Chip Oscilloscope' [patent_app_type] => utility [patent_app_number] => 13/048770 [patent_app_country] => US [patent_app_date] => 2011-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5135 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0234/20110234282.pdf [firstpage_image] =>[orig_patent_app_number] => 13048770 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/048770
Method And Circuit For Testing And Characterizing High Speed Signals Using An ON-Chip Oscilloscope Mar 14, 2011 Abandoned
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