Search

Ana J. Picon-feliciano

Examiner (ID: 3342, Phone: (571)272-5252 , Office: P/2482 )

Most Active Art Unit
2482
Art Unit(s)
2482
Total Applications
463
Issued Applications
290
Pending Applications
56
Abandoned Applications
137

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19580804 [patent_doc_number] => 12146912 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-11-19 [patent_title] => Clock gating circuits and methods for dual-edge-triggered applications [patent_app_type] => utility [patent_app_number] => 18/308486 [patent_app_country] => US [patent_app_date] => 2023-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9885 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18308486 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/308486
Clock gating circuits and methods for dual-edge-triggered applications Apr 26, 2023 Issued
Array ( [id] => 19375329 [patent_doc_number] => 12066894 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-20 [patent_title] => Storage system [patent_app_type] => utility [patent_app_number] => 18/138179 [patent_app_country] => US [patent_app_date] => 2023-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 17134 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18138179 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/138179
Storage system Apr 23, 2023 Issued
Array ( [id] => 18568381 [patent_doc_number] => 20230258717 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-17 [patent_title] => DECOMPRESSION CIRCUIT, CIRCUIT GENERATION METHOD, AND IC CHIP [patent_app_type] => utility [patent_app_number] => 18/304691 [patent_app_country] => US [patent_app_date] => 2023-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6260 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18304691 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/304691
Decompression circuit, circuit generation method, and IC chip Apr 20, 2023 Issued
Array ( [id] => 18579582 [patent_doc_number] => 11736126 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-08-22 [patent_title] => Double factor correction turbo decoding method based on simulated annealing algorithm [patent_app_type] => utility [patent_app_number] => 18/302263 [patent_app_country] => US [patent_app_date] => 2023-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2821 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18302263 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/302263
Double factor correction turbo decoding method based on simulated annealing algorithm Apr 17, 2023 Issued
Array ( [id] => 19444262 [patent_doc_number] => 12094548 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-09-17 [patent_title] => Diagnosing faults in memory periphery circuitry [patent_app_type] => utility [patent_app_number] => 18/134198 [patent_app_country] => US [patent_app_date] => 2023-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9206 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18134198 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/134198
Diagnosing faults in memory periphery circuitry Apr 12, 2023 Issued
Array ( [id] => 18729110 [patent_doc_number] => 20230343405 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-26 [patent_title] => RANDOM ACCESS MEMORY AND CORRESPONDING METHOD FOR MANAGING A RANDOM ACCESS MEMORY [patent_app_type] => utility [patent_app_number] => 18/300091 [patent_app_country] => US [patent_app_date] => 2023-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15559 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -31 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18300091 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/300091
Random access memory and corresponding method for managing a random access memory Apr 12, 2023 Issued
Array ( [id] => 19781303 [patent_doc_number] => 12230341 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-18 [patent_title] => Semiconductor device performing data read operation and controller controlling the same [patent_app_type] => utility [patent_app_number] => 18/300289 [patent_app_country] => US [patent_app_date] => 2023-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9814 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18300289 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/300289
Semiconductor device performing data read operation and controller controlling the same Apr 12, 2023 Issued
Array ( [id] => 19035663 [patent_doc_number] => 20240085478 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-14 [patent_title] => WAFER-LEVEL MULTI-DEVICE TESTER AND SYSTEM INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/299265 [patent_app_country] => US [patent_app_date] => 2023-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4764 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18299265 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/299265
Wafer-level multi-device tester and system including the same preliminary class Apr 11, 2023 Issued
Array ( [id] => 19639910 [patent_doc_number] => 12170528 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-17 [patent_title] => Method and apparatus for data decoding in communication or broadcasting system [patent_app_type] => utility [patent_app_number] => 18/299250 [patent_app_country] => US [patent_app_date] => 2023-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 37849 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18299250 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/299250
Method and apparatus for data decoding in communication or broadcasting system Apr 11, 2023 Issued
Array ( [id] => 18881388 [patent_doc_number] => 20240004757 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-04 [patent_title] => ELECTRONIC DEVICE MANAGING CORRECTED ERROR AND OPERATING METHOD OF ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 18/295457 [patent_app_country] => US [patent_app_date] => 2023-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11029 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18295457 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/295457
Electronic device managing corrected error and operating method of electronic device Apr 3, 2023 Issued
Array ( [id] => 19369154 [patent_doc_number] => 12061233 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-13 [patent_title] => Method and circuit for performing error detection on a clock gated register signal [patent_app_type] => utility [patent_app_number] => 18/193509 [patent_app_country] => US [patent_app_date] => 2023-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 16649 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18193509 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/193509
Method and circuit for performing error detection on a clock gated register signal Mar 29, 2023 Issued
Array ( [id] => 19485381 [patent_doc_number] => 20240333423 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => SYSTEMS AND METHODS OF INITIATING RETRANSMISSION REQUESTS [patent_app_type] => utility [patent_app_number] => 18/192239 [patent_app_country] => US [patent_app_date] => 2023-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7663 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18192239 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/192239
Systems and methods of initiating retransmission requests Mar 28, 2023 Issued
Array ( [id] => 19487873 [patent_doc_number] => 12107605 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-10-01 [patent_title] => Application-specific hardware device for decoding non-binary polar codes [patent_app_type] => utility [patent_app_number] => 18/126798 [patent_app_country] => US [patent_app_date] => 2023-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 11213 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18126798 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/126798
Application-specific hardware device for decoding non-binary polar codes Mar 26, 2023 Issued
Array ( [id] => 20214525 [patent_doc_number] => 12411171 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-09 [patent_title] => Built-in self-test enhancements [patent_app_type] => utility [patent_app_number] => 18/189859 [patent_app_country] => US [patent_app_date] => 2023-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 5703 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18189859 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/189859
Built-in self-test enhancements Mar 23, 2023 Issued
Array ( [id] => 20214525 [patent_doc_number] => 12411171 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-09 [patent_title] => Built-in self-test enhancements [patent_app_type] => utility [patent_app_number] => 18/189859 [patent_app_country] => US [patent_app_date] => 2023-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 5703 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18189859 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/189859
Built-in self-test enhancements Mar 23, 2023 Issued
Array ( [id] => 19393594 [patent_doc_number] => 20240283464 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-22 [patent_title] => ROBUSTNESS WHEN USING APPLICATION LAYER FORWARD ERROR CORRECTION (AL-FEC) IN AN ATSC3 RECEIVER [patent_app_type] => utility [patent_app_number] => 18/186776 [patent_app_country] => US [patent_app_date] => 2023-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5675 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18186776 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/186776
ROBUSTNESS WHEN USING APPLICATION LAYER FORWARD ERROR CORRECTION (AL-FEC) IN AN ATSC3 RECEIVER Mar 19, 2023 Abandoned
Array ( [id] => 19292673 [patent_doc_number] => 12032023 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-07-09 [patent_title] => Bit-corrector circuits for photonic circuits with cascaded photonic gates [patent_app_type] => utility [patent_app_number] => 18/120308 [patent_app_country] => US [patent_app_date] => 2023-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 7383 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18120308 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/120308
Bit-corrector circuits for photonic circuits with cascaded photonic gates Mar 9, 2023 Issued
Array ( [id] => 18813605 [patent_doc_number] => 20230387942 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => MEMORY SYSTEM AND METHOD OF CONTROLLING NONVOLATILE MEMORY [patent_app_type] => utility [patent_app_number] => 18/180481 [patent_app_country] => US [patent_app_date] => 2023-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7697 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18180481 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/180481
Memory system and method of controlling nonvolatile memory Mar 7, 2023 Issued
Array ( [id] => 19147274 [patent_doc_number] => 20240146330 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-02 [patent_title] => SOFT DECISION-BASED LOW-COMPLEXITY DECODING METHOD AND COMPUTING DEVICE FOR PERFORMING THE METHOD [patent_app_type] => utility [patent_app_number] => 18/113756 [patent_app_country] => US [patent_app_date] => 2023-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5708 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18113756 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/113756
Soft decision-based low-complexity decoding method and computing device for performing the method Feb 23, 2023 Issued
Array ( [id] => 19275539 [patent_doc_number] => 12025662 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-07-02 [patent_title] => Analog built-in self-test scheme for high volume power management integrated circuit products [patent_app_type] => utility [patent_app_number] => 18/113547 [patent_app_country] => US [patent_app_date] => 2023-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6584 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18113547 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/113547
Analog built-in self-test scheme for high volume power management integrated circuit products Feb 22, 2023 Issued
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