Search

Ana M. Fortuna

Examiner (ID: 179, Phone: (571)272-1141 , Office: P/1779 )

Most Active Art Unit
1723
Art Unit(s)
1723, 1797, 1306, 1777, 1779
Total Applications
2474
Issued Applications
1919
Pending Applications
142
Abandoned Applications
416

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18481291 [patent_doc_number] => 11695046 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-04 [patent_title] => Semiconductor device with reduced contact resistance [patent_app_type] => utility [patent_app_number] => 17/370551 [patent_app_country] => US [patent_app_date] => 2021-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 12062 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17370551 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/370551
Semiconductor device with reduced contact resistance Jul 7, 2021 Issued
Array ( [id] => 17188731 [patent_doc_number] => 20210335616 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-28 [patent_title] => CONTACT STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/370684 [patent_app_country] => US [patent_app_date] => 2021-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5884 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17370684 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/370684
Contact structure Jul 7, 2021 Issued
Array ( [id] => 19468414 [patent_doc_number] => 20240322084 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => SEMICONDUCTOR LIGHT-EMITTING ELEMENT, AND DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 18/573895 [patent_app_country] => US [patent_app_date] => 2021-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18210 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18573895 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/573895
SEMICONDUCTOR LIGHT-EMITTING ELEMENT, AND DISPLAY DEVICE Jul 4, 2021 Pending
Array ( [id] => 17159053 [patent_doc_number] => 20210320104 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-14 [patent_title] => METHOD OF FORMING SEMICONDUCTOR STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/357986 [patent_app_country] => US [patent_app_date] => 2021-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3534 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17357986 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/357986
Method of forming semiconductor structure Jun 24, 2021 Issued
Array ( [id] => 17318756 [patent_doc_number] => 20210407806 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-30 [patent_title] => LATERAL TRANSISTOR WITH SELF-ALIGNED BODY IMPLANT [patent_app_type] => utility [patent_app_number] => 17/357369 [patent_app_country] => US [patent_app_date] => 2021-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5580 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17357369 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/357369
Lateral transistor with self-aligned body implant Jun 23, 2021 Issued
Array ( [id] => 18857268 [patent_doc_number] => 11854863 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-26 [patent_title] => Semiconductor device including an isolation region having an edge being covered and manufacturing method for the same [patent_app_type] => utility [patent_app_number] => 17/357828 [patent_app_country] => US [patent_app_date] => 2021-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 8530 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17357828 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/357828
Semiconductor device including an isolation region having an edge being covered and manufacturing method for the same Jun 23, 2021 Issued
Array ( [id] => 18528732 [patent_doc_number] => 11715736 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-01 [patent_title] => Semiconductor devices with gate isolation structures and methods of manufacturing thereof [patent_app_type] => utility [patent_app_number] => 17/355418 [patent_app_country] => US [patent_app_date] => 2021-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 41 [patent_no_of_words] => 18656 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17355418 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/355418
Semiconductor devices with gate isolation structures and methods of manufacturing thereof Jun 22, 2021 Issued
Array ( [id] => 18464351 [patent_doc_number] => 11688645 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-27 [patent_title] => Structure and formation method of semiconductor device with fin structures [patent_app_type] => utility [patent_app_number] => 17/350282 [patent_app_country] => US [patent_app_date] => 2021-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 24 [patent_no_of_words] => 6947 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17350282 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/350282
Structure and formation method of semiconductor device with fin structures Jun 16, 2021 Issued
Array ( [id] => 18481287 [patent_doc_number] => 11695042 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-04 [patent_title] => Transistor contacts and methods of forming the same [patent_app_type] => utility [patent_app_number] => 17/344049 [patent_app_country] => US [patent_app_date] => 2021-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 57 [patent_no_of_words] => 12128 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17344049 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/344049
Transistor contacts and methods of forming the same Jun 9, 2021 Issued
Array ( [id] => 17115582 [patent_doc_number] => 20210296179 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-23 [patent_title] => MULTI-GATE DEVICE AND RELATED METHODS [patent_app_type] => utility [patent_app_number] => 17/303771 [patent_app_country] => US [patent_app_date] => 2021-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11102 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17303771 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/303771
Multi-gate device and related methods Jun 6, 2021 Issued
Array ( [id] => 19781603 [patent_doc_number] => 12230641 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-18 [patent_title] => Display panel, manufacturing method thereof, and display device [patent_app_type] => utility [patent_app_number] => 17/613173 [patent_app_country] => US [patent_app_date] => 2021-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3658 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17613173 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/613173
Display panel, manufacturing method thereof, and display device Jun 2, 2021 Issued
Array ( [id] => 18625753 [patent_doc_number] => 11758820 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-12 [patent_title] => Protective passivation layer for magnetic tunnel junctions [patent_app_type] => utility [patent_app_number] => 17/335717 [patent_app_country] => US [patent_app_date] => 2021-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 24 [patent_no_of_words] => 7038 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17335717 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/335717
Protective passivation layer for magnetic tunnel junctions May 31, 2021 Issued
Array ( [id] => 18040425 [patent_doc_number] => 20220384642 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-01 [patent_title] => INTEGRATED CIRCUIT STRUCTURE AND METHOD FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/333635 [patent_app_country] => US [patent_app_date] => 2021-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11490 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17333635 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/333635
Integrated circuit structure and method for forming the same May 27, 2021 Issued
Array ( [id] => 18024540 [patent_doc_number] => 20220376039 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-24 [patent_title] => LOW LEAKAGE ESD MOSFET [patent_app_type] => utility [patent_app_number] => 17/326685 [patent_app_country] => US [patent_app_date] => 2021-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4222 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17326685 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/326685
Low leakage ESD MOSFET May 20, 2021 Issued
Array ( [id] => 18507544 [patent_doc_number] => 11705371 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-18 [patent_title] => Semiconductor devices having merged source/drain features and methods of fabrication thereof [patent_app_type] => utility [patent_app_number] => 17/308552 [patent_app_country] => US [patent_app_date] => 2021-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 51 [patent_no_of_words] => 15077 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17308552 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/308552
Semiconductor devices having merged source/drain features and methods of fabrication thereof May 4, 2021 Issued
Array ( [id] => 18236131 [patent_doc_number] => 11600699 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-07 [patent_title] => Semiconductor device structure integrating air gaps and methods of forming the same [patent_app_type] => utility [patent_app_number] => 17/308258 [patent_app_country] => US [patent_app_date] => 2021-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 41 [patent_no_of_words] => 10035 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17308258 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/308258
Semiconductor device structure integrating air gaps and methods of forming the same May 4, 2021 Issued
Array ( [id] => 17174430 [patent_doc_number] => 20210328101 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-21 [patent_title] => NANO-PHOTONICS REFLECTOR FOR LED EMITTERS [patent_app_type] => utility [patent_app_number] => 17/246398 [patent_app_country] => US [patent_app_date] => 2021-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3023 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17246398 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/246398
Nano-photonics reflector for LED emitters Apr 29, 2021 Issued
Array ( [id] => 17448573 [patent_doc_number] => 20220069078 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/242823 [patent_app_country] => US [patent_app_date] => 2021-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12022 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17242823 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/242823
Semiconductor device having an air gap between gate electrode and source/drain pattern Apr 27, 2021 Issued
Array ( [id] => 18088784 [patent_doc_number] => 11538923 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-27 [patent_title] => Method for etching back hard mask layer on tops of dummy polysilicon gates in gate last process [patent_app_type] => utility [patent_app_number] => 17/242940 [patent_app_country] => US [patent_app_date] => 2021-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 7180 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 451 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17242940 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/242940
Method for etching back hard mask layer on tops of dummy polysilicon gates in gate last process Apr 27, 2021 Issued
Array ( [id] => 18520896 [patent_doc_number] => 11710791 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-25 [patent_title] => Semiconductor structure with inversion layer between stress layer and protection layer and fabrication method thereof [patent_app_type] => utility [patent_app_number] => 17/227682 [patent_app_country] => US [patent_app_date] => 2021-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 21 [patent_no_of_words] => 9308 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17227682 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/227682
Semiconductor structure with inversion layer between stress layer and protection layer and fabrication method thereof Apr 11, 2021 Issued
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