Search

Andre C. Stevenson

Examiner (ID: 17977, Phone: (571)272-1683 , Office: P/2816 )

Most Active Art Unit
2812
Art Unit(s)
2816, 2899, 2817, 2812
Total Applications
1740
Issued Applications
1530
Pending Applications
127
Abandoned Applications
125

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20235729 [patent_doc_number] => 20250293048 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-18 [patent_title] => LARGE-AREA/WAFER-SCALE CMOS-COMPATIBLE 2D-MATERIAL INTERCALATION DOPING TOOLS, PROCESSES, AND METHODS, INCLUDING INTERCALATION DOPING OF SYNTHESIZED AND PATTERNED GRAPHENE [patent_app_type] => utility [patent_app_number] => 19/224621 [patent_app_country] => US [patent_app_date] => 2025-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5627 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19224621 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/224621
LARGE-AREA/WAFER-SCALE CMOS-COMPATIBLE 2D-MATERIAL INTERCALATION DOPING TOOLS, PROCESSES, AND METHODS, INCLUDING INTERCALATION DOPING OF SYNTHESIZED AND PATTERNED GRAPHENE May 29, 2025 Pending
Array ( [id] => 19935038 [patent_doc_number] => 12308246 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-05-20 [patent_title] => Method for manufacturing semiconductor device [patent_app_type] => utility [patent_app_number] => 19/047173 [patent_app_country] => US [patent_app_date] => 2025-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 0 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 336 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19047173 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/047173
Method for manufacturing semiconductor device Feb 5, 2025 Issued
Array ( [id] => 20291351 [patent_doc_number] => 20250316594 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-09 [patent_title] => SEMICONDUCTOR DEVICE INCLUDING BACKSIDE CONTACT STRUCTURE FORMED BASED ON WIDE PLACEHOLDER STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/887789 [patent_app_country] => US [patent_app_date] => 2024-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4240 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18887789 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/887789
SEMICONDUCTOR DEVICE INCLUDING BACKSIDE CONTACT STRUCTURE FORMED BASED ON WIDE PLACEHOLDER STRUCTURE Sep 16, 2024 Pending
Array ( [id] => 19467951 [patent_doc_number] => 20240321621 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => FAN-OUT INTERCONNECT STRUCTURE AND METHODS FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/733107 [patent_app_country] => US [patent_app_date] => 2024-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4996 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18733107 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/733107
FAN-OUT INTERCONNECT STRUCTURE AND METHODS FORMING THE SAME Jun 3, 2024 Pending
Array ( [id] => 19467919 [patent_doc_number] => 20240321589 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => PROCESSES TO DEPOSIT AMORPHOUS-SILICON ETCH PROTECTION LINER [patent_app_type] => utility [patent_app_number] => 18/680496 [patent_app_country] => US [patent_app_date] => 2024-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7550 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18680496 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/680496
PROCESSES TO DEPOSIT AMORPHOUS-SILICON ETCH PROTECTION LINER May 30, 2024 Pending
Array ( [id] => 19421101 [patent_doc_number] => 20240297225 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-05 [patent_title] => METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/664595 [patent_app_country] => US [patent_app_date] => 2024-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10601 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18664595 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/664595
Method of manufacturing a semiconductor device and a semiconductor device May 14, 2024 Issued
Array ( [id] => 19407220 [patent_doc_number] => 20240290731 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-29 [patent_title] => WARPAGE-REDUCING SEMICONDUCTOR STRUCTURE AND FABRICATING METHOD OF THE SAME [patent_app_type] => utility [patent_app_number] => 18/660179 [patent_app_country] => US [patent_app_date] => 2024-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3028 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18660179 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/660179
Warpage-reducing semiconductor structure and fabricating method of the same May 8, 2024 Issued
Array ( [id] => 20244273 [patent_doc_number] => 12424605 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-23 [patent_title] => Hybrid bonding with uniform pattern density [patent_app_type] => utility [patent_app_number] => 18/640167 [patent_app_country] => US [patent_app_date] => 2024-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18640167 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/640167
Hybrid bonding with uniform pattern density Apr 18, 2024 Issued
Array ( [id] => 20244273 [patent_doc_number] => 12424605 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-23 [patent_title] => Hybrid bonding with uniform pattern density [patent_app_type] => utility [patent_app_number] => 18/640167 [patent_app_country] => US [patent_app_date] => 2024-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18640167 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/640167
Hybrid bonding with uniform pattern density Apr 18, 2024 Issued
Array ( [id] => 20119622 [patent_doc_number] => 12369361 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-22 [patent_title] => Integrated circuit including transistors and a method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 18/634295 [patent_app_country] => US [patent_app_date] => 2024-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 21 [patent_no_of_words] => 989 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18634295 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/634295
Integrated circuit including transistors and a method of manufacturing the same Apr 11, 2024 Issued
Array ( [id] => 19364319 [patent_doc_number] => 20240266353 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-08 [patent_title] => GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING DEPOPULATED CHANNEL STRUCTURES USING BOTTOM-UP APPROACH [patent_app_type] => utility [patent_app_number] => 18/625061 [patent_app_country] => US [patent_app_date] => 2024-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15160 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18625061 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/625061
Gate-all-around integrated circuit structures having depopulated channel structures using bottom-up approach Apr 1, 2024 Issued
Array ( [id] => 19285720 [patent_doc_number] => 20240222197 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => METHOD FOR FORMING A CRYSTALLINE PROTECTIVE POLYSILICON LAYER [patent_app_type] => utility [patent_app_number] => 18/609875 [patent_app_country] => US [patent_app_date] => 2024-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5187 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18609875 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/609875
METHOD FOR FORMING A CRYSTALLINE PROTECTIVE POLYSILICON LAYER Mar 18, 2024 Pending
Array ( [id] => 19407100 [patent_doc_number] => 20240290611 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-29 [patent_title] => SYSTEMS AND METHODS FOR DEPOSITING LOW-K DIELECTRIC FILMS [patent_app_type] => utility [patent_app_number] => 18/609238 [patent_app_country] => US [patent_app_date] => 2024-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5263 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18609238 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/609238
SYSTEMS AND METHODS FOR DEPOSITING LOW-K DIELECTRIC FILMS Mar 18, 2024 Issued
Array ( [id] => 19364184 [patent_doc_number] => 20240266218 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-08 [patent_title] => INTEGRATED CIRCUIT STRUCTURE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/606335 [patent_app_country] => US [patent_app_date] => 2024-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15291 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18606335 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/606335
INTEGRATED CIRCUIT STRUCTURE AND MANUFACTURING METHOD THEREOF Mar 14, 2024 Pending
Array ( [id] => 19271539 [patent_doc_number] => 20240215246 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => METHODS OF FORMING MICROELECTRONIC DEVICES WITH NITROGEN-RICH INSULATIVE STRUCTURES, AND RELATED MEMORY DEVICES AND ELECTRONIC SYSTEMS [patent_app_type] => utility [patent_app_number] => 18/596580 [patent_app_country] => US [patent_app_date] => 2024-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13995 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18596580 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/596580
METHODS OF FORMING MICROELECTRONIC DEVICES WITH NITROGEN-RICH INSULATIVE STRUCTURES, AND RELATED MEMORY DEVICES AND ELECTRONIC SYSTEMS Mar 4, 2024 Pending
Array ( [id] => 19208020 [patent_doc_number] => 20240179919 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-30 [patent_title] => VERTICAL THIN-FILM TRANSISTOR AND APPLICATION AS BIT-LINE CONNECTOR FOR 3-DIMENSIONAL MEMORY ARRAYS [patent_app_type] => utility [patent_app_number] => 18/436365 [patent_app_country] => US [patent_app_date] => 2024-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11232 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18436365 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/436365
Vertical thin-film transistor and application as bit-line connector for 3-dimensional memory arrays Feb 7, 2024 Issued
Array ( [id] => 19765913 [patent_doc_number] => 12224214 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-11 [patent_title] => Method of fabricating a semiconductor device [patent_app_type] => utility [patent_app_number] => 18/416585 [patent_app_country] => US [patent_app_date] => 2024-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 20 [patent_no_of_words] => 5596 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18416585 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/416585
Method of fabricating a semiconductor device Jan 17, 2024 Issued
Array ( [id] => 19161317 [patent_doc_number] => 20240154024 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-09 [patent_title] => FORMATION OF TRANSISTOR GATES [patent_app_type] => utility [patent_app_number] => 18/403523 [patent_app_country] => US [patent_app_date] => 2024-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13953 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18403523 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/403523
Formation of transistor gates Jan 2, 2024 Issued
Array ( [id] => 19116340 [patent_doc_number] => 20240128090 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-18 [patent_title] => METHOD FOR FABRICATING LAYER STRUCTURE HAVING TARGET TOPOLOGICAL PROFILE [patent_app_type] => utility [patent_app_number] => 18/530759 [patent_app_country] => US [patent_app_date] => 2023-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14725 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18530759 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/530759
Method for fabricating layer structure having target topological profile Dec 5, 2023 Issued
Array ( [id] => 19349154 [patent_doc_number] => 20240258118 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => LARGE-AREA WAFER-SCALE CMOS-COMPATIBLE 2D-MATERIAL INTERCALATION DOPING TOOLS, PROCESSES, AND METHODS, INCLUDING DOPING OF SYNTHESIZED GRAPHENE [patent_app_type] => utility [patent_app_number] => 18/527043 [patent_app_country] => US [patent_app_date] => 2023-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11250 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18527043 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/527043
LARGE-AREA WAFER-SCALE CMOS-COMPATIBLE 2D-MATERIAL INTERCALATION DOPING TOOLS, PROCESSES, AND METHODS, INCLUDING DOPING OF SYNTHESIZED GRAPHENE Nov 30, 2023 Pending
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