
Andre C. Stevenson
Examiner (ID: 7041, Phone: (571)272-1683 , Office: P/2816 )
| Most Active Art Unit | 2812 |
| Art Unit(s) | 2817, 2816, 2812, 2899 |
| Total Applications | 1766 |
| Issued Applications | 1549 |
| Pending Applications | 118 |
| Abandoned Applications | 127 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 17509111
[patent_doc_number] => 20220102214
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-03-31
[patent_title] => MANUFACTURING METHOD OF DEVICE CHIP
[patent_app_type] => utility
[patent_app_number] => 17/446744
[patent_app_country] => US
[patent_app_date] => 2021-09-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5788
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -2
[patent_words_short_claim] => 266
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17446744
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/446744 | Manufacturing method of device chip | Sep 1, 2021 | Issued |
Array
(
[id] => 20260746
[patent_doc_number] => 12433117
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-09-30
[patent_title] => Display substrate, preparation method therefor, and display apparatus
[patent_app_type] => utility
[patent_app_number] => 17/787604
[patent_app_country] => US
[patent_app_date] => 2021-09-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 13
[patent_no_of_words] => 12378
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 200
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17787604
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/787604 | Display substrate, preparation method therefor, and display apparatus | Sep 1, 2021 | Issued |
Array
(
[id] => 19168485
[patent_doc_number] => 11984398
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-05-14
[patent_title] => Semiconductor structure and manufacturing method thereof
[patent_app_type] => utility
[patent_app_number] => 17/465744
[patent_app_country] => US
[patent_app_date] => 2021-09-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 15
[patent_no_of_words] => 5156
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 193
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17465744
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/465744 | Semiconductor structure and manufacturing method thereof | Sep 1, 2021 | Issued |
Array
(
[id] => 18225001
[patent_doc_number] => 20230063995
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-03-02
[patent_title] => PARTIAL METAL GRAIN SIZE CONTROL TO IMPROVE CMP LOADING EFFECT
[patent_app_type] => utility
[patent_app_number] => 17/459885
[patent_app_country] => US
[patent_app_date] => 2021-08-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10455
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 122
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17459885
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/459885 | Partial metal grain size control to improve CMP loading effect | Aug 26, 2021 | Issued |
Array
(
[id] => 19277461
[patent_doc_number] => 12027594
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-07-02
[patent_title] => Method of manufacturing a semiconductor device and a semiconductor device
[patent_app_type] => utility
[patent_app_number] => 17/460097
[patent_app_country] => US
[patent_app_date] => 2021-08-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 62
[patent_no_of_words] => 10576
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 169
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17460097
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/460097 | Method of manufacturing a semiconductor device and a semiconductor device | Aug 26, 2021 | Issued |
Array
(
[id] => 18223892
[patent_doc_number] => 20230062886
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-03-02
[patent_title] => PASSIVATION STRUCTURE FOR A THIN FILM TRANSISTOR
[patent_app_type] => utility
[patent_app_number] => 17/412359
[patent_app_country] => US
[patent_app_date] => 2021-08-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7740
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 71
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17412359
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/412359 | Passivation structure for a thin film transistor | Aug 25, 2021 | Issued |
Array
(
[id] => 18688300
[patent_doc_number] => 11784043
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-10-10
[patent_title] => Formation of SiN thin films
[patent_app_type] => utility
[patent_app_number] => 17/406919
[patent_app_country] => US
[patent_app_date] => 2021-08-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 15
[patent_no_of_words] => 15423
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17406919
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/406919 | Formation of SiN thin films | Aug 18, 2021 | Issued |
Array
(
[id] => 18196736
[patent_doc_number] => 20230050255
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-02-16
[patent_title] => SEAM REMOVAL IN HIGH ASPECT RATIO GAP-FILL
[patent_app_type] => utility
[patent_app_number] => 17/401574
[patent_app_country] => US
[patent_app_date] => 2021-08-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6469
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17401574
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/401574 | Seam removal in high aspect ratio gap-fill | Aug 12, 2021 | Issued |
Array
(
[id] => 19913687
[patent_doc_number] => 12289920
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-04-29
[patent_title] => Semiconductor device and method for manufacturing the same
[patent_app_type] => utility
[patent_app_number] => 17/442141
[patent_app_country] => US
[patent_app_date] => 2021-08-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 12
[patent_no_of_words] => 3409
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 264
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17442141
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/442141 | Semiconductor device and method for manufacturing the same | Aug 10, 2021 | Issued |
Array
(
[id] => 18197681
[patent_doc_number] => 20230051200
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-02-16
[patent_title] => SEAM-FREE GAPFILL DEPOSITION
[patent_app_type] => utility
[patent_app_number] => 17/399702
[patent_app_country] => US
[patent_app_date] => 2021-08-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6717
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 68
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17399702
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/399702 | SEAM-FREE GAPFILL DEPOSITION | Aug 10, 2021 | Pending |
Array
(
[id] => 17295330
[patent_doc_number] => 20210391169
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-12-16
[patent_title] => METHOD FOR FORMING SILICON DIOXIDE FILM AND METHOD FOR FORMING METAL GATE
[patent_app_type] => utility
[patent_app_number] => 17/398075
[patent_app_country] => US
[patent_app_date] => 2021-08-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2846
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 68
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17398075
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/398075 | Method for forming silicon dioxide film and method for forming metal gate | Aug 9, 2021 | Issued |
Array
(
[id] => 17373758
[patent_doc_number] => 20220028810
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-01-27
[patent_title] => SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING SEMICONDUCTOR STRUCTURE
[patent_app_type] => utility
[patent_app_number] => 17/398127
[patent_app_country] => US
[patent_app_date] => 2021-08-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4071
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -11
[patent_words_short_claim] => 71
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17398127
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/398127 | Semiconductor structure and method for forming semiconductor structure | Aug 9, 2021 | Issued |
Array
(
[id] => 19277236
[patent_doc_number] => 12027368
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-07-02
[patent_title] => Method for fabricating semiconductor device
[patent_app_type] => utility
[patent_app_number] => 17/397482
[patent_app_country] => US
[patent_app_date] => 2021-08-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 72
[patent_figures_cnt] => 84
[patent_no_of_words] => 17150
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 244
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17397482
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/397482 | Method for fabricating semiconductor device | Aug 8, 2021 | Issued |
Array
(
[id] => 19244480
[patent_doc_number] => 12014932
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-06-18
[patent_title] => Memory, substrate structure of the memory, and method for preparing the substrate structure of the memory
[patent_app_type] => utility
[patent_app_number] => 17/396690
[patent_app_country] => US
[patent_app_date] => 2021-08-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 5159
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 201
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17396690
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/396690 | Memory, substrate structure of the memory, and method for preparing the substrate structure of the memory | Aug 6, 2021 | Issued |
Array
(
[id] => 17247160
[patent_doc_number] => 20210366905
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-11-25
[patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/393025
[patent_app_country] => US
[patent_app_date] => 2021-08-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11381
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 117
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17393025
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/393025 | Semiconductor device and method for fabricating the same | Aug 2, 2021 | Issued |
Array
(
[id] => 19356894
[patent_doc_number] => 12057350
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-08-06
[patent_title] => Forming a protective layer to prevent formation of leakage paths
[patent_app_type] => utility
[patent_app_number] => 17/387447
[patent_app_country] => US
[patent_app_date] => 2021-07-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 5797
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17387447
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/387447 | Forming a protective layer to prevent formation of leakage paths | Jul 27, 2021 | Issued |
Array
(
[id] => 19093922
[patent_doc_number] => 11955387
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-04-09
[patent_title] => Method of fabricating a semiconductor device
[patent_app_type] => utility
[patent_app_number] => 17/386323
[patent_app_country] => US
[patent_app_date] => 2021-07-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 20
[patent_no_of_words] => 5575
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 190
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17386323
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/386323 | Method of fabricating a semiconductor device | Jul 26, 2021 | Issued |
Array
(
[id] => 17217856
[patent_doc_number] => 20210351194
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-11-11
[patent_title] => MANUFACTURING METHOD FOR MEMORY STRUCTURE
[patent_app_type] => utility
[patent_app_number] => 17/381202
[patent_app_country] => US
[patent_app_date] => 2021-07-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4194
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 278
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17381202
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/381202 | Manufacturing method for memory structure | Jul 20, 2021 | Issued |
Array
(
[id] => 19444706
[patent_doc_number] => 12094998
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-09-17
[patent_title] => Group III nitride based LED structures including multiple quantum wells with barrier-well unit interface layers
[patent_app_type] => utility
[patent_app_number] => 17/377833
[patent_app_country] => US
[patent_app_date] => 2021-07-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 20
[patent_no_of_words] => 18217
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 117
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17377833
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/377833 | Group III nitride based LED structures including multiple quantum wells with barrier-well unit interface layers | Jul 15, 2021 | Issued |
Array
(
[id] => 19704879
[patent_doc_number] => 12198926
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-01-14
[patent_title] => Silicon nitride films having reduced interfacial strain
[patent_app_type] => utility
[patent_app_number] => 17/377135
[patent_app_country] => US
[patent_app_date] => 2021-07-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 38
[patent_no_of_words] => 6903
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17377135
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/377135 | Silicon nitride films having reduced interfacial strain | Jul 14, 2021 | Issued |