Andre C. Stevenson

Array ( [id] => 18431795 [patent_doc_number] => 11677027 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-13 [patent_title] => Semiconductor device and method [patent_app_type] => utility [patent_app_number] => 17/371953 [patent_app_country] => US [patent_app_date] => 2021-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 36 [patent_no_of_words] => 10897 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17371953 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17509182 [patent_doc_number] => 20220102285 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => CMP SAFE ALIGNMENT MARK [patent_app_type] => utility [patent_app_number] => 17/369841 [patent_app_country] => US [patent_app_date] => 2021-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5127 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17369841 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19244540 [patent_doc_number] => 12014995 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-18 [patent_title] => Warpage-reducing semiconductor structure and fabricating method of the same [patent_app_type] => utility [patent_app_number] => 17/369936 [patent_app_country] => US [patent_app_date] => 2021-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2966 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17369936 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17373635 [patent_doc_number] => 20220028687 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-27 [patent_title] => METHOD OF DEPOSITING THIN FILM AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME [patent_app_type] => utility [patent_app_number] => 17/360982 [patent_app_country] => US [patent_app_date] => 2021-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3480 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17360982 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19523959 [patent_doc_number] => 12125699 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-22 [patent_title] => Selective carbon deposition on top and bottom surfaces of semiconductor substrates [patent_app_type] => utility [patent_app_number] => 17/359947 [patent_app_country] => US [patent_app_date] => 2021-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 9768 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17359947 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19027177 [patent_doc_number] => 11926524 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-03-12 [patent_title] => Methods, apparatus, and systems for fabricating solution-based conductive 2D and 3D electronic circuits [patent_app_type] => utility [patent_app_number] => 17/354474 [patent_app_country] => US [patent_app_date] => 2021-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 119 [patent_figures_cnt] => 176 [patent_no_of_words] => 20018 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17354474 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17795548 [patent_doc_number] => 20220254640 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-11 [patent_title] => Amorphous Silicon-Based Scavenging And Sealing EOT [patent_app_type] => utility [patent_app_number] => 17/347786 [patent_app_country] => US [patent_app_date] => 2021-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8428 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17347786 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19844166 [patent_doc_number] => 12256582 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-18 [patent_title] => Display panel, manufacturing method and display device [patent_app_type] => utility [patent_app_number] => 17/770253 [patent_app_country] => US [patent_app_date] => 2021-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4602 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17770253 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19507955 [patent_doc_number] => 12119386 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-15 [patent_title] => Conductive capping for work function layer and method forming same [patent_app_type] => utility [patent_app_number] => 17/340818 [patent_app_country] => US [patent_app_date] => 2021-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 7227 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17340818 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17855485 [patent_doc_number] => 20220285528 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-08 [patent_title] => FORMATION OF TRANSISTOR GATES [patent_app_type] => utility [patent_app_number] => 17/340037 [patent_app_country] => US [patent_app_date] => 2021-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13936 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17340037 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17765084 [patent_doc_number] => 20220238697 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-28 [patent_title] => Reducing K Values of Dielectric Films Through Anneal [patent_app_type] => utility [patent_app_number] => 17/333592 [patent_app_country] => US [patent_app_date] => 2021-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8745 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17333592 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18447059 [patent_doc_number] => 11682635 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-20 [patent_title] => Systems and methods for the use of fraud prevention fluid to prevent chip fraud [patent_app_type] => utility [patent_app_number] => 17/327152 [patent_app_country] => US [patent_app_date] => 2021-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 13876 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17327152 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19206348 [patent_doc_number] => 20240178247 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-30 [patent_title] => HERMETIC PACKAGE DEVICE AND DEVICE MODULE [patent_app_type] => utility [patent_app_number] => 18/551178 [patent_app_country] => US [patent_app_date] => 2021-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6666 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18551178 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17985945 [patent_doc_number] => 20220351982 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-03 [patent_title] => PROCESSES TO DEPOSIT AMORPHOUS-SILICON ETCH PROTECTION LINER [patent_app_type] => utility [patent_app_number] => 17/246209 [patent_app_country] => US [patent_app_date] => 2021-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7525 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17246209 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17319218 [patent_doc_number] => 20210408268 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-30 [patent_title] => Method for Manufacturing Semiconductor Device [patent_app_type] => utility [patent_app_number] => 17/224406 [patent_app_country] => US [patent_app_date] => 2021-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4750 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17224406 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18343494 [patent_doc_number] => 11640978 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-02 [patent_title] => Low-k feature formation processes and structures formed thereby [patent_app_type] => utility [patent_app_number] => 17/222303 [patent_app_country] => US [patent_app_date] => 2021-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 7410 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17222303 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17536633 [patent_doc_number] => 20220115242 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-14 [patent_title] => SEMICONDUCTOR STRUCTURE AND FORMING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/218886 [patent_app_country] => US [patent_app_date] => 2021-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12049 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17218886 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17509108 [patent_doc_number] => 20220102211 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => INTEGRATED CIRCUIT STRUCTURE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/214417 [patent_app_country] => US [patent_app_date] => 2021-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15281 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17214417 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19741425 [patent_doc_number] => 12218273 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-04 [patent_title] => ULED chip, uLED substrate and method for manufacturing the same, el inspection method for uLED substrate, and el inspection apparatus [patent_app_type] => utility [patent_app_number] => 17/776127 [patent_app_country] => US [patent_app_date] => 2021-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 20 [patent_no_of_words] => 12516 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17776127 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17145344 [patent_doc_number] => 20210313357 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-07 [patent_title] => PHOTODETECTOR, DISPLAY SUBSTRATE, AND METHOD OF MANUFACTURING PHOTODETECTOR [patent_app_type] => utility [patent_app_number] => 17/204057 [patent_app_country] => US [patent_app_date] => 2021-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6353 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17204057 [rel_patent_id] =>[rel_patent_doc_number] =>)