
Andre C. Stevenson
Examiner (ID: 7041, Phone: (571)272-1683 , Office: P/2816 )
| Most Active Art Unit | 2812 |
| Art Unit(s) | 2817, 2816, 2812, 2899 |
| Total Applications | 1766 |
| Issued Applications | 1549 |
| Pending Applications | 118 |
| Abandoned Applications | 127 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 15901929
[patent_doc_number] => 20200150484
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-05-14
[patent_title] => MANUFACTURING METHOD FOR LIQUID CRYSTAL DISPLAY DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/735388
[patent_app_country] => US
[patent_app_date] => 2020-01-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6860
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 123
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16735388
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/735388 | Manufacturing method for liquid crystal display device | Jan 5, 2020 | Issued |
Array
(
[id] => 16846143
[patent_doc_number] => 11018240
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-05-25
[patent_title] => Vertical field effect transistor with reduced parasitic capacitance
[patent_app_type] => utility
[patent_app_number] => 16/732463
[patent_app_country] => US
[patent_app_date] => 2020-01-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 28
[patent_figures_cnt] => 28
[patent_no_of_words] => 9361
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16732463
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/732463 | Vertical field effect transistor with reduced parasitic capacitance | Jan 1, 2020 | Issued |
Array
(
[id] => 16936623
[patent_doc_number] => 20210202512
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-07-01
[patent_title] => MEMORY STRUCTURE AND MANUFACTURING METHOD THEREFOR
[patent_app_type] => utility
[patent_app_number] => 16/731070
[patent_app_country] => US
[patent_app_date] => 2019-12-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4152
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16731070
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/731070 | Memory structure and manufacturing method therefor | Dec 30, 2019 | Issued |
Array
(
[id] => 16098597
[patent_doc_number] => 20200203285
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-06-25
[patent_title] => STAIRCASE ETCH CONTROL IN FORMING THREE-DIMENSIONAL MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/731475
[patent_app_country] => US
[patent_app_date] => 2019-12-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 15743
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16731475
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/731475 | STAIRCASE ETCH CONTROL IN FORMING THREE-DIMENSIONAL MEMORY DEVICE | Dec 30, 2019 | Abandoned |
Array
(
[id] => 16846150
[patent_doc_number] => 11018247
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2021-05-25
[patent_title] => Semiconductor device with a base link region and method therefor
[patent_app_type] => utility
[patent_app_number] => 16/727591
[patent_app_country] => US
[patent_app_date] => 2019-12-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 10781
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16727591
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/727591 | Semiconductor device with a base link region and method therefor | Dec 25, 2019 | Issued |
Array
(
[id] => 16820109
[patent_doc_number] => 11004948
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-05-11
[patent_title] => Three-dimensional memory devices and methods for forming the same
[patent_app_type] => utility
[patent_app_number] => 16/727874
[patent_app_country] => US
[patent_app_date] => 2019-12-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 29
[patent_figures_cnt] => 34
[patent_no_of_words] => 21393
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16727874
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/727874 | Three-dimensional memory devices and methods for forming the same | Dec 25, 2019 | Issued |
Array
(
[id] => 16928331
[patent_doc_number] => 11049822
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2021-06-29
[patent_title] => Systems and methods for the use of fraud prevention fluid to prevent chip fraud
[patent_app_type] => utility
[patent_app_number] => 16/723725
[patent_app_country] => US
[patent_app_date] => 2019-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 27
[patent_figures_cnt] => 27
[patent_no_of_words] => 13845
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 77
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16723725
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/723725 | Systems and methods for the use of fraud prevention fluid to prevent chip fraud | Dec 19, 2019 | Issued |
Array
(
[id] => 15776267
[patent_doc_number] => 20200119151
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-04-16
[patent_title] => Low-k Feature Formation Processes and Structures Formed Thereby
[patent_app_type] => utility
[patent_app_number] => 16/715899
[patent_app_country] => US
[patent_app_date] => 2019-12-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7376
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16715899
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/715899 | Low-k feature formation processes and structures formed thereby | Dec 15, 2019 | Issued |
Array
(
[id] => 16080541
[patent_doc_number] => 20200194257
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-06-18
[patent_title] => SUBSTRATE PROCESSING METHOD
[patent_app_type] => utility
[patent_app_number] => 16/714218
[patent_app_country] => US
[patent_app_date] => 2019-12-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8642
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -6
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16714218
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/714218 | Substrate processing method | Dec 12, 2019 | Issued |
Array
(
[id] => 16120667
[patent_doc_number] => 20200212356
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-07-02
[patent_title] => Electroluminescent Display Apparatus
[patent_app_type] => utility
[patent_app_number] => 16/714211
[patent_app_country] => US
[patent_app_date] => 2019-12-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 15230
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -21
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16714211
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/714211 | Electroluminescent display apparatus | Dec 12, 2019 | Issued |
Array
(
[id] => 16081471
[patent_doc_number] => 20200194722
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-06-18
[patent_title] => LIGHTING APPARATUS USING ORGANIC LIGHT EMITTING DIODE
[patent_app_type] => utility
[patent_app_number] => 16/711229
[patent_app_country] => US
[patent_app_date] => 2019-12-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13864
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16711229
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/711229 | Lighting apparatus using organic light emitting diode | Dec 10, 2019 | Issued |
Array
(
[id] => 15739409
[patent_doc_number] => 20200108592
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-04-09
[patent_title] => WAFER DEBONDING SYSTEM AND METHOD
[patent_app_type] => utility
[patent_app_number] => 16/710348
[patent_app_country] => US
[patent_app_date] => 2019-12-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6550
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16710348
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/710348 | Wafer debonding system and method | Dec 10, 2019 | Issued |
Array
(
[id] => 15993045
[patent_doc_number] => 20200172393
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-06-04
[patent_title] => METHODS FOR WAFER BONDING
[patent_app_type] => utility
[patent_app_number] => 16/695673
[patent_app_country] => US
[patent_app_date] => 2019-11-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5420
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 66
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16695673
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/695673 | Methods for wafer bonding | Nov 25, 2019 | Issued |
Array
(
[id] => 16163311
[patent_doc_number] => 20200219888
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-07-09
[patent_title] => METHOD FOR FABRICATING SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/692731
[patent_app_country] => US
[patent_app_date] => 2019-11-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2634
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 62
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16692731
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/692731 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE | Nov 21, 2019 | Abandoned |
Array
(
[id] => 16000905
[patent_doc_number] => 20200176323
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-06-04
[patent_title] => SEMICONDUCTOR ARRANGEMENT AND METHOD OF MANUFACTURE
[patent_app_type] => utility
[patent_app_number] => 16/687999
[patent_app_country] => US
[patent_app_date] => 2019-11-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8185
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16687999
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/687999 | Semiconductor arrangement and method of manufacture | Nov 18, 2019 | Issued |
Array
(
[id] => 17922173
[patent_doc_number] => 11465397
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2022-10-11
[patent_title] => Fabrication of high-resolution graphene-based flexible electronics via polymer casting
[patent_app_type] => utility
[patent_app_number] => 16/687347
[patent_app_country] => US
[patent_app_date] => 2019-11-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 48
[patent_figures_cnt] => 54
[patent_no_of_words] => 11845
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 59
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16687347
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/687347 | Fabrication of high-resolution graphene-based flexible electronics via polymer casting | Nov 17, 2019 | Issued |
Array
(
[id] => 17048175
[patent_doc_number] => 11101365
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-08-24
[patent_title] => Method for fabricating semiconductor device and semiconductor device fabricated by the same
[patent_app_type] => utility
[patent_app_number] => 16/684146
[patent_app_country] => US
[patent_app_date] => 2019-11-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 2
[patent_no_of_words] => 6093
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 150
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16684146
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/684146 | Method for fabricating semiconductor device and semiconductor device fabricated by the same | Nov 13, 2019 | Issued |
Array
(
[id] => 17093106
[patent_doc_number] => 11121304
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-09-14
[patent_title] => Junction fabrication method for forming qubits
[patent_app_type] => utility
[patent_app_number] => 16/684423
[patent_app_country] => US
[patent_app_date] => 2019-11-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 25
[patent_no_of_words] => 5826
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 251
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16684423
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/684423 | Junction fabrication method for forming qubits | Nov 13, 2019 | Issued |
Array
(
[id] => 17803450
[patent_doc_number] => 11417763
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-08-16
[patent_title] => Integrated circuit including transistors and a method of manufacturing the same
[patent_app_type] => utility
[patent_app_number] => 16/682512
[patent_app_country] => US
[patent_app_date] => 2019-11-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 21
[patent_no_of_words] => 6092
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 237
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16682512
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/682512 | Integrated circuit including transistors and a method of manufacturing the same | Nov 12, 2019 | Issued |
Array
(
[id] => 16112491
[patent_doc_number] => 20200208268
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-07-02
[patent_title] => PLASMA ATOMIC LAYER DEPOSITION
[patent_app_type] => utility
[patent_app_number] => 16/675904
[patent_app_country] => US
[patent_app_date] => 2019-11-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7233
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16675904
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/675904 | Plasma atomic layer deposition | Nov 5, 2019 | Issued |