
Andre C. Stevenson
Examiner (ID: 7041, Phone: (571)272-1683 , Office: P/2816 )
| Most Active Art Unit | 2812 |
| Art Unit(s) | 2817, 2816, 2812, 2899 |
| Total Applications | 1766 |
| Issued Applications | 1549 |
| Pending Applications | 118 |
| Abandoned Applications | 127 |
Applications
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|---|---|---|---|
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