Search

Andre C. Stevenson

Examiner (ID: 7041, Phone: (571)272-1683 , Office: P/2816 )

Most Active Art Unit
2812
Art Unit(s)
2817, 2816, 2812, 2899
Total Applications
1766
Issued Applications
1549
Pending Applications
118
Abandoned Applications
127

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19364319 [patent_doc_number] => 20240266353 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-08 [patent_title] => GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING DEPOPULATED CHANNEL STRUCTURES USING BOTTOM-UP APPROACH [patent_app_type] => utility [patent_app_number] => 18/625061 [patent_app_country] => US [patent_app_date] => 2024-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15160 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18625061 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/625061
Gate-all-around integrated circuit structures having depopulated channel structures using bottom-up approach Apr 1, 2024 Issued
Array ( [id] => 19546545 [patent_doc_number] => 20240363581 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => WIRE BONDING APPARATUS AND SEMICONDUCTOR PACKAGE MANUFACTURED USING THE SAME [patent_app_type] => utility [patent_app_number] => 18/622131 [patent_app_country] => US [patent_app_date] => 2024-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9652 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18622131 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/622131
WIRE BONDING APPARATUS AND SEMICONDUCTOR PACKAGE MANUFACTURED USING THE SAME Mar 28, 2024 Pending
Array ( [id] => 19484222 [patent_doc_number] => 20240332264 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => PIXEL PACKAGE [patent_app_type] => utility [patent_app_number] => 18/615912 [patent_app_country] => US [patent_app_date] => 2024-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6274 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18615912 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/615912
PIXEL PACKAGE Mar 24, 2024 Pending
Array ( [id] => 20011303 [patent_doc_number] => 20250149525 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-08 [patent_title] => CHIP PACKAGE WITH ACTIVE SILICON BRIDGE [patent_app_type] => utility [patent_app_number] => 18/615918 [patent_app_country] => US [patent_app_date] => 2024-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5851 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18615918 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/615918
CHIP PACKAGE WITH ACTIVE SILICON BRIDGE Mar 24, 2024 Pending
Array ( [id] => 19285720 [patent_doc_number] => 20240222197 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => METHOD FOR FORMING A CRYSTALLINE PROTECTIVE POLYSILICON LAYER [patent_app_type] => utility [patent_app_number] => 18/609875 [patent_app_country] => US [patent_app_date] => 2024-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5187 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18609875 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/609875
Method for forming a crystalline protective polysilicon layer Mar 18, 2024 Issued
Array ( [id] => 20469405 [patent_doc_number] => 12525447 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-13 [patent_title] => Systems and methods for depositing low-k dielectric films [patent_app_type] => utility [patent_app_number] => 18/609238 [patent_app_country] => US [patent_app_date] => 2024-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 0 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18609238 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/609238
Systems and methods for depositing low-k dielectric films Mar 18, 2024 Issued
Array ( [id] => 19364184 [patent_doc_number] => 20240266218 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-08 [patent_title] => INTEGRATED CIRCUIT STRUCTURE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/606335 [patent_app_country] => US [patent_app_date] => 2024-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15291 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18606335 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/606335
INTEGRATED CIRCUIT STRUCTURE AND MANUFACTURING METHOD THEREOF Mar 14, 2024 Pending
Array ( [id] => 19271539 [patent_doc_number] => 20240215246 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => METHODS OF FORMING MICROELECTRONIC DEVICES WITH NITROGEN-RICH INSULATIVE STRUCTURES, AND RELATED MEMORY DEVICES AND ELECTRONIC SYSTEMS [patent_app_type] => utility [patent_app_number] => 18/596580 [patent_app_country] => US [patent_app_date] => 2024-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13995 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18596580 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/596580
METHODS OF FORMING MICROELECTRONIC DEVICES WITH NITROGEN-RICH INSULATIVE STRUCTURES, AND RELATED MEMORY DEVICES AND ELECTRONIC SYSTEMS Mar 4, 2024 Pending
Array ( [id] => 19208020 [patent_doc_number] => 20240179919 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-30 [patent_title] => VERTICAL THIN-FILM TRANSISTOR AND APPLICATION AS BIT-LINE CONNECTOR FOR 3-DIMENSIONAL MEMORY ARRAYS [patent_app_type] => utility [patent_app_number] => 18/436365 [patent_app_country] => US [patent_app_date] => 2024-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11232 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18436365 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/436365
Vertical thin-film transistor and application as bit-line connector for 3-dimensional memory arrays Feb 7, 2024 Issued
Array ( [id] => 19191526 [patent_doc_number] => 20240170439 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-23 [patent_title] => POWER MODULE, POWER SUPPLY CIRCUIT, AND CHIP [patent_app_type] => utility [patent_app_number] => 18/429432 [patent_app_country] => US [patent_app_date] => 2024-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10890 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18429432 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/429432
POWER MODULE, POWER SUPPLY CIRCUIT, AND CHIP Jan 31, 2024 Pending
Array ( [id] => 19765913 [patent_doc_number] => 12224214 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-11 [patent_title] => Method of fabricating a semiconductor device [patent_app_type] => utility [patent_app_number] => 18/416585 [patent_app_country] => US [patent_app_date] => 2024-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 20 [patent_no_of_words] => 5596 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18416585 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/416585
Method of fabricating a semiconductor device Jan 17, 2024 Issued
Array ( [id] => 19161317 [patent_doc_number] => 20240154024 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-09 [patent_title] => FORMATION OF TRANSISTOR GATES [patent_app_type] => utility [patent_app_number] => 18/403523 [patent_app_country] => US [patent_app_date] => 2024-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13953 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18403523 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/403523
Formation of transistor gates Jan 2, 2024 Issued
Array ( [id] => 20090952 [patent_doc_number] => 20250220888 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-03 [patent_title] => VERTICAL GATE-ALL-AROUND MEMORY DEVICE HAVING STACKED CAPACITOR STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/401962 [patent_app_country] => US [patent_app_date] => 2024-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10671 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18401962 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/401962
VERTICAL GATE-ALL-AROUND MEMORY DEVICE HAVING STACKED CAPACITOR STRUCTURE Jan 1, 2024 Pending
Array ( [id] => 19116340 [patent_doc_number] => 20240128090 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-18 [patent_title] => METHOD FOR FABRICATING LAYER STRUCTURE HAVING TARGET TOPOLOGICAL PROFILE [patent_app_type] => utility [patent_app_number] => 18/530759 [patent_app_country] => US [patent_app_date] => 2023-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14725 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18530759 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/530759
Method for fabricating layer structure having target topological profile Dec 5, 2023 Issued
Array ( [id] => 19349154 [patent_doc_number] => 20240258118 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => LARGE-AREA WAFER-SCALE CMOS-COMPATIBLE 2D-MATERIAL INTERCALATION DOPING TOOLS, PROCESSES, AND METHODS, INCLUDING DOPING OF SYNTHESIZED GRAPHENE [patent_app_type] => utility [patent_app_number] => 18/527043 [patent_app_country] => US [patent_app_date] => 2023-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11250 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18527043 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/527043
LARGE-AREA WAFER-SCALE CMOS-COMPATIBLE 2D-MATERIAL INTERCALATION DOPING TOOLS, PROCESSES, AND METHODS, INCLUDING DOPING OF SYNTHESIZED GRAPHENE Nov 30, 2023 Pending
Array ( [id] => 19054927 [patent_doc_number] => 20240096896 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-21 [patent_title] => NON-PLANAR INTEGRATED CIRCUIT STRUCTURES HAVING MITIGATED SOURCE OR DRAIN ETCH FROM REPLACEMENT GATE PROCESS [patent_app_type] => utility [patent_app_number] => 18/523637 [patent_app_country] => US [patent_app_date] => 2023-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15820 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18523637 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/523637
Non-planar integrated circuit structures having mitigated source or drain etch from replacement gate process Nov 28, 2023 Issued
Array ( [id] => 19793216 [patent_doc_number] => 12234145 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-25 [patent_title] => Methods for wafer bonding [patent_app_type] => utility [patent_app_number] => 18/513545 [patent_app_country] => US [patent_app_date] => 2023-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5435 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18513545 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/513545
Methods for wafer bonding Nov 17, 2023 Issued
Array ( [id] => 19023301 [patent_doc_number] => 20240079472 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-07 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THE SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/502110 [patent_app_country] => US [patent_app_date] => 2023-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9297 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18502110 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/502110
Semiconductor device and manufacturing method for the semiconductor device Nov 5, 2023 Issued
Array ( [id] => 18977243 [patent_doc_number] => 20240057335 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-15 [patent_title] => INTEGRATED ASSEMBLIES AND METHODS OF FORMING INTEGRATED ASSEMBLIES [patent_app_type] => utility [patent_app_number] => 18/384455 [patent_app_country] => US [patent_app_date] => 2023-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7628 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18384455 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/384455
Integrated assemblies and methods of forming integrated assemblies Oct 26, 2023 Issued
Array ( [id] => 18991117 [patent_doc_number] => 20240063086 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-22 [patent_title] => Monatomic Single-Entity Baseplate Structure Employing a Thermoplastic Polyimide Bondline Between a Silicon Substrate and a Metallic Heat Sink Having Mismatched Coefficients of Thermal [patent_app_type] => utility [patent_app_number] => 18/384052 [patent_app_country] => US [patent_app_date] => 2023-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2213 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18384052 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/384052
Monatomic Single-Entity Baseplate Structure Employing a Thermoplastic Polyimide Bondline Between a Silicon Substrate and a Metallic Heat Sink Having Mismatched Coefficients of Thermal Oct 25, 2023 Pending
Menu