Search

Andre C. Stevenson

Examiner (ID: 7041, Phone: (571)272-1683 , Office: P/2816 )

Most Active Art Unit
2812
Art Unit(s)
2817, 2816, 2812, 2899
Total Applications
1766
Issued Applications
1549
Pending Applications
118
Abandoned Applications
127

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16280266 [patent_doc_number] => 10763307 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-09-01 [patent_title] => Stackable cross-point phase-change material memory array with a resistive liner [patent_app_type] => utility [patent_app_number] => 16/380618 [patent_app_country] => US [patent_app_date] => 2019-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 20 [patent_no_of_words] => 8927 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16380618 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/380618
Stackable cross-point phase-change material memory array with a resistive liner Apr 9, 2019 Issued
Array ( [id] => 14676699 [patent_doc_number] => 20190237464 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-01 [patent_title] => NEGATIVE CAPACITANCE FINFET AND METHOD OF FABRICATING THEREOF [patent_app_type] => utility [patent_app_number] => 16/380818 [patent_app_country] => US [patent_app_date] => 2019-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12405 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16380818 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/380818
Negative capacitance finFET and method of fabricating thereof Apr 9, 2019 Issued
Array ( [id] => 16379409 [patent_doc_number] => 20200328252 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-15 [patent_title] => MAGNETORESISTIVE DEVICES AND METHODS THEREFOR [patent_app_type] => utility [patent_app_number] => 16/380207 [patent_app_country] => US [patent_app_date] => 2019-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11440 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16380207 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/380207
Magnetoresistive devices and methods therefor Apr 9, 2019 Issued
Array ( [id] => 16348320 [patent_doc_number] => 20200312971 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-01 [patent_title] => GATE STACKS FOR FINFET TRANSISTORS [patent_app_type] => utility [patent_app_number] => 16/369517 [patent_app_country] => US [patent_app_date] => 2019-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8677 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16369517 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/369517
Gate stacks for FinFET transistors Mar 28, 2019 Issued
Array ( [id] => 16348325 [patent_doc_number] => 20200312976 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-01 [patent_title] => TRANSISTOR DEVICE WITH VARIOUSLY CONFORMAL GATE DIELECTRIC LAYERS [patent_app_type] => utility [patent_app_number] => 16/363632 [patent_app_country] => US [patent_app_date] => 2019-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9321 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16363632 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/363632
Transistor device with variously conformal gate dielectric layers Mar 24, 2019 Issued
Array ( [id] => 16679500 [patent_doc_number] => 20210068266 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-04 [patent_title] => GLASS WIRING SUBSTRATE AND COMPONENT-MOUNTED GLASS WIRING SUBSTRATE [patent_app_type] => utility [patent_app_number] => 17/040361 [patent_app_country] => US [patent_app_date] => 2019-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12015 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17040361 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/040361
GLASS WIRING SUBSTRATE AND COMPONENT-MOUNTED GLASS WIRING SUBSTRATE Mar 12, 2019 Abandoned
Array ( [id] => 17668287 [patent_doc_number] => 11361991 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-14 [patent_title] => Method for Si gap fill by PECVD [patent_app_type] => utility [patent_app_number] => 16/975794 [patent_app_country] => US [patent_app_date] => 2019-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2735 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16975794 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/975794
Method for Si gap fill by PECVD Mar 6, 2019 Issued
Array ( [id] => 16560603 [patent_doc_number] => 20210005752 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-07 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/978262 [patent_app_country] => US [patent_app_date] => 2019-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 31737 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16978262 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/978262
Semiconductor device and method for manufacturing semiconductor device Mar 4, 2019 Issued
Array ( [id] => 14475727 [patent_doc_number] => 20190189511 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-20 [patent_title] => CONTACT STRUCTURE AND ASSOCIATED METHOD FOR FLASH MEMORY [patent_app_type] => utility [patent_app_number] => 16/269811 [patent_app_country] => US [patent_app_date] => 2019-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10780 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16269811 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/269811
Contact structure and associated method for flash memory Feb 6, 2019 Issued
Array ( [id] => 16264783 [patent_doc_number] => 10756231 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-25 [patent_title] => Group III nitride based LED structures including multiple quantum wells with barrier-well unit interface layers [patent_app_type] => utility [patent_app_number] => 16/267636 [patent_app_country] => US [patent_app_date] => 2019-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 20 [patent_no_of_words] => 18166 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16267636 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/267636
Group III nitride based LED structures including multiple quantum wells with barrier-well unit interface layers Feb 4, 2019 Issued
Array ( [id] => 16210394 [patent_doc_number] => 20200243384 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-30 [patent_title] => LASER MARKED CODE PATTERN FOR REPRESENTING TRACING NUMBER OF CHIP [patent_app_type] => utility [patent_app_number] => 16/257223 [patent_app_country] => US [patent_app_date] => 2019-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2970 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16257223 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/257223
Laser marked code pattern for representing tracing number of chip Jan 24, 2019 Issued
Array ( [id] => 16210396 [patent_doc_number] => 20200243386 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-30 [patent_title] => METHOD FOR FABRICATING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/258389 [patent_app_country] => US [patent_app_date] => 2019-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2052 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16258389 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/258389
METHOD FOR FABRICATING SEMICONDUCTOR DEVICE Jan 24, 2019 Abandoned
Array ( [id] => 16020849 [patent_doc_number] => 20200185268 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-11 [patent_title] => METHOD OF FORMING FINE INTERCONNECTION FOR A SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/257021 [patent_app_country] => US [patent_app_date] => 2019-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3414 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16257021 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/257021
Method of forming fine interconnection for a semiconductor device Jan 23, 2019 Issued
Array ( [id] => 14686867 [patent_doc_number] => 20190242548 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-08 [patent_title] => OPTICAL UNIT AND OPTICAL APPARATUS [patent_app_type] => utility [patent_app_number] => 16/256024 [patent_app_country] => US [patent_app_date] => 2019-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7747 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16256024 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/256024
Optical unit and optical apparatus Jan 23, 2019 Issued
Array ( [id] => 16210489 [patent_doc_number] => 20200243479 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-30 [patent_title] => PRECISION ALIGNMENT OF MULTI-CHIP HIGH DENSITY INTERCONNECTS [patent_app_type] => utility [patent_app_number] => 16/256344 [patent_app_country] => US [patent_app_date] => 2019-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2641 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16256344 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/256344
Precision alignment of multi-chip high density interconnects Jan 23, 2019 Issued
Array ( [id] => 15822925 [patent_doc_number] => 10636658 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-04-28 [patent_title] => Methods of forming patterns, and methods of patterning conductive structures of integrated assemblies [patent_app_type] => utility [patent_app_number] => 16/255458 [patent_app_country] => US [patent_app_date] => 2019-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 27 [patent_no_of_words] => 6162 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16255458 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/255458
Methods of forming patterns, and methods of patterning conductive structures of integrated assemblies Jan 22, 2019 Issued
Array ( [id] => 16191237 [patent_doc_number] => 20200232086 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-23 [patent_title] => BACKSIDE METAL FORMATION METHODS AND SYSTEMS [patent_app_type] => utility [patent_app_number] => 16/254904 [patent_app_country] => US [patent_app_date] => 2019-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3448 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16254904 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/254904
Backside metal formation methods and systems Jan 22, 2019 Issued
Array ( [id] => 14631271 [patent_doc_number] => 20190229005 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-25 [patent_title] => CUTTING METHOD OF WORKPIECE [patent_app_type] => utility [patent_app_number] => 16/252838 [patent_app_country] => US [patent_app_date] => 2019-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7143 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -1 [patent_words_short_claim] => 288 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16252838 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/252838
Cutting method of workpiece Jan 20, 2019 Issued
Array ( [id] => 14677395 [patent_doc_number] => 20190237812 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-01 [patent_title] => LITHIATION OF ELECTRODES FOR CYLINDRICAL ENERGY STORAGE DEVICES AND METHOD OF MAKING SAME [patent_app_type] => utility [patent_app_number] => 16/252149 [patent_app_country] => US [patent_app_date] => 2019-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4082 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16252149 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/252149
Lithiation of electrodes for cylindrical energy storage devices and method of making same Jan 17, 2019 Issued
Array ( [id] => 14904895 [patent_doc_number] => 20190296213 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-26 [patent_title] => VERTICAL TRANSMON QUBIT DEVICE [patent_app_type] => utility [patent_app_number] => 16/248141 [patent_app_country] => US [patent_app_date] => 2019-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14553 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16248141 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/248141
Vertical transmon qubit device Jan 14, 2019 Issued
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