
Andre C. Stevenson
Examiner (ID: 7041, Phone: (571)272-1683 , Office: P/2816 )
| Most Active Art Unit | 2812 |
| Art Unit(s) | 2817, 2816, 2812, 2899 |
| Total Applications | 1766 |
| Issued Applications | 1549 |
| Pending Applications | 118 |
| Abandoned Applications | 127 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 11943637
[patent_doc_number] => 20170247788
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-08-31
[patent_title] => 'SHADOW MASK, FILM FORMING SYSTEM USING SHADOW MASK AND METHOD OF MANUFACTURING A DISPLAY DEVICE'
[patent_app_type] => utility
[patent_app_number] => 15/425224
[patent_app_country] => US
[patent_app_date] => 2017-02-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2509
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15425224
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/425224 | Shadow mask, film forming system using shadow mask and method of manufacturing a display device | Feb 5, 2017 | Issued |
Array
(
[id] => 15422797
[patent_doc_number] => 10544313
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-01-28
[patent_title] => Method and apparatus of applying light and heat to quantum dots to increase quantum yield
[patent_app_type] => utility
[patent_app_number] => 15/425920
[patent_app_country] => US
[patent_app_date] => 2017-02-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 19
[patent_no_of_words] => 8759
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15425920
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/425920 | Method and apparatus of applying light and heat to quantum dots to increase quantum yield | Feb 5, 2017 | Issued |
Array
(
[id] => 13201533
[patent_doc_number] => 10115687
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-10-30
[patent_title] => Method of pattern placement correction
[patent_app_type] => utility
[patent_app_number] => 15/424366
[patent_app_country] => US
[patent_app_date] => 2017-02-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 19
[patent_no_of_words] => 3875
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 136
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15424366
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/424366 | Method of pattern placement correction | Feb 2, 2017 | Issued |
Array
(
[id] => 12457410
[patent_doc_number] => 09985008
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-05-29
[patent_title] => Method of fabricating a semiconductor package
[patent_app_type] => utility
[patent_app_number] => 15/423611
[patent_app_country] => US
[patent_app_date] => 2017-02-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 12
[patent_no_of_words] => 5291
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 138
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15423611
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/423611 | Method of fabricating a semiconductor package | Feb 2, 2017 | Issued |
Array
(
[id] => 12499227
[patent_doc_number] => 09997704
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-06-12
[patent_title] => Scaled cross bar array with undercut electrode
[patent_app_type] => utility
[patent_app_number] => 15/416407
[patent_app_country] => US
[patent_app_date] => 2017-01-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 13
[patent_no_of_words] => 6659
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 61
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15416407
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/416407 | Scaled cross bar array with undercut electrode | Jan 25, 2017 | Issued |
Array
(
[id] => 13878583
[patent_doc_number] => 20190035632
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-01-31
[patent_title] => TRIMMING OPTICAL DEVICE STRUCTURES
[patent_app_type] => utility
[patent_app_number] => 16/072013
[patent_app_country] => US
[patent_app_date] => 2017-01-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2407
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16072013
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/072013 | Trimming optical device structures | Jan 22, 2017 | Issued |
Array
(
[id] => 13878575
[patent_doc_number] => 20190035628
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-01-31
[patent_title] => METHOD AND STRUCTURE FOR REDUCING SUBSTRATE FRAGILITY
[patent_app_type] => utility
[patent_app_number] => 16/071654
[patent_app_country] => US
[patent_app_date] => 2017-01-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3133
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16071654
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/071654 | METHOD AND STRUCTURE FOR REDUCING SUBSTRATE FRAGILITY | Jan 18, 2017 | Abandoned |
Array
(
[id] => 12534624
[patent_doc_number] => 10008398
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-06-26
[patent_title] => Substrate thinning apparatus, method of thinning substrate by using the same, and method of fabricating semiconductor package
[patent_app_type] => utility
[patent_app_number] => 15/369138
[patent_app_country] => US
[patent_app_date] => 2016-12-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 24
[patent_no_of_words] => 9129
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15369138
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/369138 | Substrate thinning apparatus, method of thinning substrate by using the same, and method of fabricating semiconductor package | Dec 4, 2016 | Issued |
Array
(
[id] => 11673697
[patent_doc_number] => 20170162420
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-06-08
[patent_title] => 'METHOD OF PROCESSING WAFER'
[patent_app_type] => utility
[patent_app_number] => 15/367558
[patent_app_country] => US
[patent_app_date] => 2016-12-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 4087
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15367558
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/367558 | Method of processing wafer | Dec 1, 2016 | Issued |
Array
(
[id] => 12457989
[patent_doc_number] => 09985202
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-05-29
[patent_title] => Method of fabricating memory device
[patent_app_type] => utility
[patent_app_number] => 15/365977
[patent_app_country] => US
[patent_app_date] => 2016-12-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 6272
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 90
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15365977
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/365977 | Method of fabricating memory device | Nov 30, 2016 | Issued |
Array
(
[id] => 12778831
[patent_doc_number] => 20180151445
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-05-31
[patent_title] => FORMING A PROTECTIVE LAYER TO PREVENT FORMATION OF LEAKAGE PATHS
[patent_app_type] => utility
[patent_app_number] => 15/364488
[patent_app_country] => US
[patent_app_date] => 2016-11-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5698
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15364488
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/364488 | Forming a protective layer to prevent formation of leakage paths | Nov 29, 2016 | Issued |
Array
(
[id] => 13121647
[patent_doc_number] => 10079179
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-09-18
[patent_title] => Wafer processing method
[patent_app_type] => utility
[patent_app_number] => 15/365406
[patent_app_country] => US
[patent_app_date] => 2016-11-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 10
[patent_no_of_words] => 4417
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 297
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15365406
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/365406 | Wafer processing method | Nov 29, 2016 | Issued |
Array
(
[id] => 14955507
[patent_doc_number] => 10439033
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-10-08
[patent_title] => Semiconductor devices
[patent_app_type] => utility
[patent_app_number] => 15/350425
[patent_app_country] => US
[patent_app_date] => 2016-11-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 30
[patent_no_of_words] => 11617
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 130
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15350425
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/350425 | Semiconductor devices | Nov 13, 2016 | Issued |
Array
(
[id] => 11592942
[patent_doc_number] => 20170117354
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-04-27
[patent_title] => 'MOSFET ACTIVE AREA AND EDGE TERMINATION AREA CHARGE BALANCE'
[patent_app_type] => utility
[patent_app_number] => 15/339678
[patent_app_country] => US
[patent_app_date] => 2016-10-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 4383
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15339678
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/339678 | MOSFET active area and edge termination area charge balance | Oct 30, 2016 | Issued |
Array
(
[id] => 11439198
[patent_doc_number] => 20170040219
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-02-09
[patent_title] => 'III-V, SiGe, or Ge Base Lateral Bipolar Transistor and CMOS Hybrid Technology'
[patent_app_type] => utility
[patent_app_number] => 15/332207
[patent_app_country] => US
[patent_app_date] => 2016-10-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5915
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15332207
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/332207 | III-V, SiGe, or Ge base lateral bipolar transistor and CMOS hybrid technology | Oct 23, 2016 | Issued |
Array
(
[id] => 12417243
[patent_doc_number] => 09972697
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-05-15
[patent_title] => Method to improve reliability of replacement gate device
[patent_app_type] => utility
[patent_app_number] => 15/267887
[patent_app_country] => US
[patent_app_date] => 2016-09-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 12
[patent_no_of_words] => 3513
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15267887
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/267887 | Method to improve reliability of replacement gate device | Sep 15, 2016 | Issued |
Array
(
[id] => 12516441
[patent_doc_number] => 10002948
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-06-19
[patent_title] => FinFET having highly doped source and drain regions
[patent_app_type] => utility
[patent_app_number] => 15/265261
[patent_app_country] => US
[patent_app_date] => 2016-09-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 15
[patent_no_of_words] => 8747
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 61
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15265261
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/265261 | FinFET having highly doped source and drain regions | Sep 13, 2016 | Issued |
Array
(
[id] => 11510379
[patent_doc_number] => 09601546
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2017-03-21
[patent_title] => 'Scaled cross bar array with undercut electrode'
[patent_app_type] => utility
[patent_app_number] => 15/262722
[patent_app_country] => US
[patent_app_date] => 2016-09-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 13
[patent_no_of_words] => 6883
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15262722
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/262722 | Scaled cross bar array with undercut electrode | Sep 11, 2016 | Issued |
Array
(
[id] => 12376074
[patent_doc_number] => 09960252
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-05-01
[patent_title] => Method to improve reliability of replacement gate device
[patent_app_type] => utility
[patent_app_number] => 15/258597
[patent_app_country] => US
[patent_app_date] => 2016-09-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 12
[patent_no_of_words] => 3401
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 119
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15258597
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/258597 | Method to improve reliability of replacement gate device | Sep 6, 2016 | Issued |
Array
(
[id] => 15442913
[patent_doc_number] => 20200035640
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-01-30
[patent_title] => SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/095387
[patent_app_country] => US
[patent_app_date] => 2016-09-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3503
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 145
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16095387
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/095387 | Semiconductor device | Sep 6, 2016 | Issued |