Search

Andre C. Stevenson

Examiner (ID: 7041, Phone: (571)272-1683 , Office: P/2816 )

Most Active Art Unit
2812
Art Unit(s)
2817, 2816, 2812, 2899
Total Applications
1766
Issued Applications
1549
Pending Applications
118
Abandoned Applications
127

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 13402955 [patent_doc_number] => 20180253020 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-06 [patent_title] => RELATIVE POSITION MEASUREMENT BASED ALIGNMENT SYSTEM, DOUBLE WORKPIECE STAGE SYSTEM AND MEASUREMENT SYSTEM [patent_app_type] => utility [patent_app_number] => 15/756272 [patent_app_country] => US [patent_app_date] => 2016-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3869 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15756272 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/756272
Relative position measurement based alignment system, double workpiece stage system and measurement system Aug 25, 2016 Issued
Array ( [id] => 12396288 [patent_doc_number] => 09966351 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-05-08 [patent_title] => Grid array connection device and method [patent_app_type] => utility [patent_app_number] => 15/246382 [patent_app_country] => US [patent_app_date] => 2016-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 3775 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15246382 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/246382
Grid array connection device and method Aug 23, 2016 Issued
Array ( [id] => 11544911 [patent_doc_number] => 20170098736 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-06 [patent_title] => 'MATERIAL LAYER STACK, LIGHT EMITTING ELEMENT, LIGHT EMITTING PACKAGE, AND METHOD OF FABRICATING LIGHT EMITTING ELEMENT' [patent_app_type] => utility [patent_app_number] => 15/241316 [patent_app_country] => US [patent_app_date] => 2016-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 17131 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15241316 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/241316
Material layer stack, light emitting element, light emitting package, and method of fabricating light emitting element Aug 18, 2016 Issued
Array ( [id] => 11918464 [patent_doc_number] => 09786656 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-10-10 [patent_title] => 'Integration of bipolar transistor into complimentary metal-oxide-semiconductor process' [patent_app_type] => utility [patent_app_number] => 15/241348 [patent_app_country] => US [patent_app_date] => 2016-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 20 [patent_no_of_words] => 3860 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15241348 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/241348
Integration of bipolar transistor into complimentary metal-oxide-semiconductor process Aug 18, 2016 Issued
Array ( [id] => 11874963 [patent_doc_number] => 09746732 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-29 [patent_title] => 'Display device' [patent_app_type] => utility [patent_app_number] => 15/240520 [patent_app_country] => US [patent_app_date] => 2016-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5336 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15240520 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/240520
Display device Aug 17, 2016 Issued
Array ( [id] => 14230093 [patent_doc_number] => 20190127219 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-02 [patent_title] => SUBSTRATE ASSEMBLY AND RELATED METHODS [patent_app_type] => utility [patent_app_number] => 16/094411 [patent_app_country] => US [patent_app_date] => 2016-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11347 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16094411 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/094411
Substrate assembly and related methods Jul 21, 2016 Issued
Array ( [id] => 11125531 [patent_doc_number] => 20160322506 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-03 [patent_title] => 'MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/205026 [patent_app_country] => US [patent_app_date] => 2016-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 27186 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15205026 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/205026
Manufacturing method of semiconductor device Jul 7, 2016 Issued
Array ( [id] => 12250188 [patent_doc_number] => 09922971 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-20 [patent_title] => 'Integration of analog transistor' [patent_app_type] => utility [patent_app_number] => 15/204338 [patent_app_country] => US [patent_app_date] => 2016-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 5334 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15204338 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/204338
Integration of analog transistor Jul 6, 2016 Issued
Array ( [id] => 11132335 [patent_doc_number] => 20160329310 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-10 [patent_title] => 'Methods of Forming Conductive and Insulating Layers' [patent_app_type] => utility [patent_app_number] => 15/202349 [patent_app_country] => US [patent_app_date] => 2016-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 12946 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15202349 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/202349
Methods of forming conductive and insulating layers Jul 4, 2016 Issued
Array ( [id] => 13302693 [patent_doc_number] => 20180202883 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-19 [patent_title] => SEMICONDUCTOR DEVICE, MECHANICAL QUANTITY MEASURING DEVICE, AND SEMICONDUCTOR DEVICE FABRICATING METHOD [patent_app_type] => utility [patent_app_number] => 15/742809 [patent_app_country] => US [patent_app_date] => 2016-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5990 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15742809 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/742809
Semiconductor device, mechanical quantity measuring device, and semiconductor device fabricating method Jun 29, 2016 Issued
Array ( [id] => 11740483 [patent_doc_number] => 09705080 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-07-11 [patent_title] => 'Forming self-aligned conductive lines for resistive random access memories' [patent_app_type] => utility [patent_app_number] => 15/182202 [patent_app_country] => US [patent_app_date] => 2016-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 1988 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15182202 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/182202
Forming self-aligned conductive lines for resistive random access memories Jun 13, 2016 Issued
Array ( [id] => 16521616 [patent_doc_number] => 10872841 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-22 [patent_title] => Ceramic metal circuit board and semiconductor device using the same [patent_app_type] => utility [patent_app_number] => 15/742829 [patent_app_country] => US [patent_app_date] => 2016-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 9222 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15742829 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/742829
Ceramic metal circuit board and semiconductor device using the same May 31, 2016 Issued
Array ( [id] => 14738785 [patent_doc_number] => 10388804 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-20 [patent_title] => Solar cell and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 15/166593 [patent_app_country] => US [patent_app_date] => 2016-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 12411 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15166593 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/166593
Solar cell and method of manufacturing the same May 26, 2016 Issued
Array ( [id] => 11862098 [patent_doc_number] => 09741790 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-22 [patent_title] => 'Method for creating the high voltage complementary BJT with lateral collector on bulk substrate with resurf effect' [patent_app_type] => utility [patent_app_number] => 15/098452 [patent_app_country] => US [patent_app_date] => 2016-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2283 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15098452 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/098452
Method for creating the high voltage complementary BJT with lateral collector on bulk substrate with resurf effect Apr 13, 2016 Issued
Array ( [id] => 11014375 [patent_doc_number] => 20160211329 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-21 [patent_title] => 'METHOD OF FORMING AN ISOLATION STRUCTURE IN A WELL OF A SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 15/083844 [patent_app_country] => US [patent_app_date] => 2016-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3889 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15083844 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/083844
Method of forming an isolation structure in a well of a substrate Mar 28, 2016 Issued
Array ( [id] => 11014295 [patent_doc_number] => 20160211248 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-21 [patent_title] => 'Hybrid Bonding with Uniform Pattern Density' [patent_app_type] => utility [patent_app_number] => 15/082216 [patent_app_country] => US [patent_app_date] => 2016-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4921 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15082216 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/082216
Hybrid bonding with uniform pattern density Mar 27, 2016 Issued
Array ( [id] => 12047564 [patent_doc_number] => 09825174 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-11-21 [patent_title] => 'FinFET with dielectric isolated channel' [patent_app_type] => utility [patent_app_number] => 15/080901 [patent_app_country] => US [patent_app_date] => 2016-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2273 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15080901 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/080901
FinFET with dielectric isolated channel Mar 24, 2016 Issued
Array ( [id] => 15139909 [patent_doc_number] => 10483443 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-19 [patent_title] => Light emitting device and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 15/078321 [patent_app_country] => US [patent_app_date] => 2016-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 26 [patent_no_of_words] => 14110 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15078321 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/078321
Light emitting device and manufacturing method thereof Mar 22, 2016 Issued
Array ( [id] => 11007086 [patent_doc_number] => 20160204038 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-14 [patent_title] => 'METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH IMPROVED IMPLANTATION PROCESSES' [patent_app_type] => utility [patent_app_number] => 15/074483 [patent_app_country] => US [patent_app_date] => 2016-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4068 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15074483 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/074483
Methods for fabricating integrated circuits with improved implantation processes Mar 17, 2016 Issued
Array ( [id] => 14125551 [patent_doc_number] => 10249639 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-02 [patent_title] => Semiconductor memory device [patent_app_type] => utility [patent_app_number] => 15/070825 [patent_app_country] => US [patent_app_date] => 2016-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4696 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 267 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15070825 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/070825
Semiconductor memory device Mar 14, 2016 Issued
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