Search

Andre C. Stevenson

Examiner (ID: 7041, Phone: (571)272-1683 , Office: P/2816 )

Most Active Art Unit
2812
Art Unit(s)
2817, 2816, 2812, 2899
Total Applications
1766
Issued Applications
1549
Pending Applications
118
Abandoned Applications
127

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10172166 [patent_doc_number] => 09202877 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-12-01 [patent_title] => 'Method for manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 13/761498 [patent_app_country] => US [patent_app_date] => 2013-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 53 [patent_no_of_words] => 32066 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13761498 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/761498
Method for manufacturing semiconductor device Feb 6, 2013 Issued
Array ( [id] => 8963613 [patent_doc_number] => 20130203214 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-08 [patent_title] => 'METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/755862 [patent_app_country] => US [patent_app_date] => 2013-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 32081 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13755862 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/755862
Method for manufacturing semiconductor device Jan 30, 2013 Issued
Array ( [id] => 10053664 [patent_doc_number] => 09093550 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-07-28 [patent_title] => 'Integrated circuits having a plurality of high-K metal gate FETs with various combinations of channel foundation structure and gate stack structure and methods of making same' [patent_app_type] => utility [patent_app_number] => 13/755887 [patent_app_country] => US [patent_app_date] => 2013-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 7781 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13755887 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/755887
Integrated circuits having a plurality of high-K metal gate FETs with various combinations of channel foundation structure and gate stack structure and methods of making same Jan 30, 2013 Issued
Array ( [id] => 10080070 [patent_doc_number] => 09117925 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-08-25 [patent_title] => 'Epitaxial process' [patent_app_type] => utility [patent_app_number] => 13/756464 [patent_app_country] => US [patent_app_date] => 2013-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 3271 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13756464 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/756464
Epitaxial process Jan 30, 2013 Issued
Array ( [id] => 9676775 [patent_doc_number] => 08815685 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-26 [patent_title] => 'Methods for fabricating integrated circuits having confined epitaxial growth regions' [patent_app_type] => utility [patent_app_number] => 13/755246 [patent_app_country] => US [patent_app_date] => 2013-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 3512 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13755246 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/755246
Methods for fabricating integrated circuits having confined epitaxial growth regions Jan 30, 2013 Issued
Array ( [id] => 9634923 [patent_doc_number] => 20140213032 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-31 [patent_title] => 'Process For Forming Resistive Switching Memory Cells Using Nano-Particles' [patent_app_type] => utility [patent_app_number] => 13/755577 [patent_app_country] => US [patent_app_date] => 2013-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 8092 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13755577 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/755577
Process for forming resistive switching memory cells using nano-particles Jan 30, 2013 Issued
Array ( [id] => 9983523 [patent_doc_number] => 09029230 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-05-12 [patent_title] => 'Conductive line routing for multi-patterning technology' [patent_app_type] => utility [patent_app_number] => 13/755326 [patent_app_country] => US [patent_app_date] => 2013-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4632 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13755326 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/755326
Conductive line routing for multi-patterning technology Jan 30, 2013 Issued
Array ( [id] => 10073513 [patent_doc_number] => 09111878 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-08-18 [patent_title] => 'Method for forming a semiconductor device assembly having a heat spreader' [patent_app_type] => utility [patent_app_number] => 13/755904 [patent_app_country] => US [patent_app_date] => 2013-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 3639 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13755904 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/755904
Method for forming a semiconductor device assembly having a heat spreader Jan 30, 2013 Issued
Array ( [id] => 9989514 [patent_doc_number] => 09034716 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-05-19 [patent_title] => 'Method of making a FinFET device' [patent_app_type] => utility [patent_app_number] => 13/756104 [patent_app_country] => US [patent_app_date] => 2013-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 3632 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13756104 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/756104
Method of making a FinFET device Jan 30, 2013 Issued
Array ( [id] => 8950685 [patent_doc_number] => 20130196466 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-01 [patent_title] => 'METHOD AND APPARATUS FOR PRODUCING A TRANSPARENT CONDUCTIVE OXIDE' [patent_app_type] => utility [patent_app_number] => 13/754613 [patent_app_country] => US [patent_app_date] => 2013-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2909 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13754613 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/754613
METHOD AND APPARATUS FOR PRODUCING A TRANSPARENT CONDUCTIVE OXIDE Jan 29, 2013 Abandoned
Array ( [id] => 11206020 [patent_doc_number] => 09435643 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-06 [patent_title] => 'Presumably defective portion decision apparatus, presumably defective portion decision method, fabrication method for semiconductor device and program' [patent_app_type] => utility [patent_app_number] => 13/754635 [patent_app_country] => US [patent_app_date] => 2013-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 31 [patent_no_of_words] => 21526 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13754635 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/754635
Presumably defective portion decision apparatus, presumably defective portion decision method, fabrication method for semiconductor device and program Jan 29, 2013 Issued
Array ( [id] => 8841566 [patent_doc_number] => 20130137194 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-30 [patent_title] => 'METHOD OF MANUFACTURING A LIGHT EMITTING DEVICE AND THIN FILM FORMING APPARATUS' [patent_app_type] => utility [patent_app_number] => 13/748890 [patent_app_country] => US [patent_app_date] => 2013-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 15867 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13748890 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/748890
Method of manufacturing a light emitting device and thin film forming apparatus Jan 23, 2013 Issued
Array ( [id] => 8825817 [patent_doc_number] => 20130126862 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-23 [patent_title] => 'METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/740313 [patent_app_country] => US [patent_app_date] => 2013-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 31578 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13740313 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/740313
Method for manufacturing semiconductor device Jan 13, 2013 Issued
Array ( [id] => 8825900 [patent_doc_number] => 20130126945 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-23 [patent_title] => 'ULTRA HIGH VOLTAGE SIGE HBT AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 13/680506 [patent_app_country] => US [patent_app_date] => 2012-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3207 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13680506 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/680506
Ultra high voltage SiGe HBT and manufacturing method thereof Nov 18, 2012 Issued
Array ( [id] => 9491192 [patent_doc_number] => 20140141598 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-22 [patent_title] => 'METHOD TO IMPROVE RELIABILITY OF REPLACEMENT GATE DEVICE' [patent_app_type] => utility [patent_app_number] => 13/680257 [patent_app_country] => US [patent_app_date] => 2012-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3556 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13680257 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/680257
Method to improve reliability of replacement gate device Nov 18, 2012 Issued
Array ( [id] => 9280905 [patent_doc_number] => 20140030873 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-30 [patent_title] => 'METHOD FOR FABRICATING PATTERNED SILICON NANOWIRE ARRAY AND SILICON MICROSTRUCTURE' [patent_app_type] => utility [patent_app_number] => 13/680301 [patent_app_country] => US [patent_app_date] => 2012-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5926 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13680301 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/680301
METHOD FOR FABRICATING PATTERNED SILICON NANOWIRE ARRAY AND SILICON MICROSTRUCTURE Nov 18, 2012 Abandoned
Array ( [id] => 11904496 [patent_doc_number] => 09773938 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-09-26 [patent_title] => 'Manufacturing method of an amorphous-silicon flat-panel X-ray sensor' [patent_app_type] => utility [patent_app_number] => 13/995424 [patent_app_country] => US [patent_app_date] => 2012-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 23 [patent_no_of_words] => 6233 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13995424 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/995424
Manufacturing method of an amorphous-silicon flat-panel X-ray sensor Oct 28, 2012 Issued
Array ( [id] => 8671070 [patent_doc_number] => 20130045608 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-21 [patent_title] => 'REDUCTION OF PORE FILL MATERIAL DEWETTING' [patent_app_type] => utility [patent_app_number] => 13/655599 [patent_app_country] => US [patent_app_date] => 2012-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8552 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13655599 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/655599
Reduction of pore fill material dewetting Oct 18, 2012 Issued
Array ( [id] => 8733244 [patent_doc_number] => 20130078813 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-03-28 [patent_title] => 'PATTERN FORMING METHOD' [patent_app_type] => utility [patent_app_number] => 13/628401 [patent_app_country] => US [patent_app_date] => 2012-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 28769 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13628401 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/628401
Pattern forming method Sep 26, 2012 Issued
Array ( [id] => 9384077 [patent_doc_number] => 20140087559 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-27 [patent_title] => 'SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD OF THE SAME' [patent_app_type] => utility [patent_app_number] => 13/628125 [patent_app_country] => US [patent_app_date] => 2012-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2585 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13628125 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/628125
SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD OF THE SAME Sep 26, 2012 Abandoned
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