
Andre C. Stevenson
Examiner (ID: 7041, Phone: (571)272-1683 , Office: P/2816 )
| Most Active Art Unit | 2812 |
| Art Unit(s) | 2817, 2816, 2812, 2899 |
| Total Applications | 1766 |
| Issued Applications | 1549 |
| Pending Applications | 118 |
| Abandoned Applications | 127 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 19679272
[patent_doc_number] => 12191144
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-01-07
[patent_title] => Semiconductor device and manufacturing method thereof
[patent_app_type] => utility
[patent_app_number] => 17/876487
[patent_app_country] => US
[patent_app_date] => 2022-07-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 71
[patent_figures_cnt] => 71
[patent_no_of_words] => 17895
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17876487
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/876487 | Semiconductor device and manufacturing method thereof | Jul 27, 2022 | Issued |
Array
(
[id] => 19046675
[patent_doc_number] => 11935795
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-03-19
[patent_title] => Method for forming a crystalline protective polysilicon layer
[patent_app_type] => utility
[patent_app_number] => 17/876442
[patent_app_country] => US
[patent_app_date] => 2022-07-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 15
[patent_no_of_words] => 5172
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17876442
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/876442 | Method for forming a crystalline protective polysilicon layer | Jul 27, 2022 | Issued |
Array
(
[id] => 17993185
[patent_doc_number] => 20220359222
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-11-10
[patent_title] => DOUBLE PATTERNING METHOD
[patent_app_type] => utility
[patent_app_number] => 17/874371
[patent_app_country] => US
[patent_app_date] => 2022-07-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5607
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 57
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17874371
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/874371 | Double patterning method | Jul 26, 2022 | Issued |
Array
(
[id] => 18024257
[patent_doc_number] => 20220375756
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-11-24
[patent_title] => Germanium Hump Reduction
[patent_app_type] => utility
[patent_app_number] => 17/814283
[patent_app_country] => US
[patent_app_date] => 2022-07-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8779
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17814283
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/814283 | Germanium hump reduction | Jul 21, 2022 | Issued |
Array
(
[id] => 18848809
[patent_doc_number] => 20230411213
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-12-21
[patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/868786
[patent_app_country] => US
[patent_app_date] => 2022-07-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4162
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 62
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17868786
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/868786 | Semiconductor device and method for fabricating the same | Jul 19, 2022 | Issued |
Array
(
[id] => 18195801
[patent_doc_number] => 20230049320
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-02-16
[patent_title] => METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/867835
[patent_app_country] => US
[patent_app_date] => 2022-07-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5598
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 117
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17867835
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/867835 | Method for manufacturing semiconductor device, and semiconductor device | Jul 18, 2022 | Issued |
Array
(
[id] => 20376835
[patent_doc_number] => 12484291
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-11-25
[patent_title] => Semiconductor device and manufacturing method thereof
[patent_app_type] => utility
[patent_app_number] => 17/868294
[patent_app_country] => US
[patent_app_date] => 2022-07-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 44
[patent_no_of_words] => 5141
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 119
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17868294
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/868294 | Semiconductor device and manufacturing method thereof | Jul 18, 2022 | Issued |
Array
(
[id] => 17985944
[patent_doc_number] => 20220351981
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-11-03
[patent_title] => ETCHING METHOD, PLASMA PROCESSING APPARATUS, SUBSTRATE PROCESSING SYSTEM, AND PROGRAM
[patent_app_type] => utility
[patent_app_number] => 17/865433
[patent_app_country] => US
[patent_app_date] => 2022-07-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 16646
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 75
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17865433
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/865433 | ETCHING METHOD, PLASMA PROCESSING APPARATUS, SUBSTRATE PROCESSING SYSTEM, AND PROGRAM | Jul 14, 2022 | Pending |
Array
(
[id] => 18008411
[patent_doc_number] => 20220367178
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-11-17
[patent_title] => SPIN ON CARBON COMPOSITION AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/864293
[patent_app_country] => US
[patent_app_date] => 2022-07-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9694
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17864293
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/864293 | Spin on carbon composition and method of manufacturing a semiconductor device | Jul 12, 2022 | Issued |
Array
(
[id] => 20776842
[patent_doc_number] => 12660539
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-06-16
[patent_title] => Apparatus for removing etch stop layers
[patent_app_type] => utility
[patent_app_number] => 17/858390
[patent_app_country] => US
[patent_app_date] => 2022-07-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 12
[patent_no_of_words] => 2369
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 339
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17858390
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/858390 | Apparatus for removing etch stop layers | Jul 5, 2022 | Issued |
Array
(
[id] => 17949475
[patent_doc_number] => 20220336494
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-10-20
[patent_title] => Integrated Assemblies and Methods of Forming Integrated Assemblies
[patent_app_type] => utility
[patent_app_number] => 17/854393
[patent_app_country] => US
[patent_app_date] => 2022-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7575
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -29
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17854393
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/854393 | Integrated assemblies and methods of forming integrated assemblies | Jun 29, 2022 | Issued |
Array
(
[id] => 18882861
[patent_doc_number] => 20240006230
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-01-04
[patent_title] => SHALLOW TRENCH ISOLATION STRUCTURE WITH NITRIDE PULLBACK BY IMPLANTATION TREATMENT
[patent_app_type] => utility
[patent_app_number] => 17/854852
[patent_app_country] => US
[patent_app_date] => 2022-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4924
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17854852
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/854852 | Shallow trench isolation structure with nitride pullback by implantation treatment | Jun 29, 2022 | Issued |
Array
(
[id] => 17900854
[patent_doc_number] => 20220310516
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-09-29
[patent_title] => CONTACT OVER ACTIVE GATE STRUCTURES WITH ETCH STOP LAYERS FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION
[patent_app_type] => utility
[patent_app_number] => 17/841479
[patent_app_country] => US
[patent_app_date] => 2022-06-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 16004
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 163
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17841479
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/841479 | Contact over active gate structures with etch stop layers for advanced integrated circuit structure fabrication | Jun 14, 2022 | Issued |
Array
(
[id] => 18840153
[patent_doc_number] => 11848232
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-12-19
[patent_title] => Method for Si gap fill by PECVD
[patent_app_type] => utility
[patent_app_number] => 17/839170
[patent_app_country] => US
[patent_app_date] => 2022-06-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 2557
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17839170
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/839170 | Method for Si gap fill by PECVD | Jun 12, 2022 | Issued |
Array
(
[id] => 19294520
[patent_doc_number] => 12033883
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-07-09
[patent_title] => Fan-out interconnect structure and methods forming the same
[patent_app_type] => utility
[patent_app_number] => 17/805557
[patent_app_country] => US
[patent_app_date] => 2022-06-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 24
[patent_no_of_words] => 4963
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17805557
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/805557 | Fan-out interconnect structure and methods forming the same | Jun 5, 2022 | Issued |
Array
(
[id] => 19399635
[patent_doc_number] => 12074021
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-08-27
[patent_title] => Semiconductor device and method of forming the same
[patent_app_type] => utility
[patent_app_number] => 17/832675
[patent_app_country] => US
[patent_app_date] => 2022-06-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 12
[patent_no_of_words] => 8365
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17832675
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/832675 | Semiconductor device and method of forming the same | Jun 4, 2022 | Issued |
Array
(
[id] => 18985402
[patent_doc_number] => 11910612
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-02-20
[patent_title] => Process for forming a vertical thin-film transistor that serves as a connector to a bit-line of a 3-dimensional memory array
[patent_app_type] => utility
[patent_app_number] => 17/804986
[patent_app_country] => US
[patent_app_date] => 2022-06-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 40
[patent_figures_cnt] => 60
[patent_no_of_words] => 11196
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 239
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17804986
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/804986 | Process for forming a vertical thin-film transistor that serves as a connector to a bit-line of a 3-dimensional memory array | May 31, 2022 | Issued |
Array
(
[id] => 19936821
[patent_doc_number] => 12310041
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-05-20
[patent_title] => Metal-insulator-metal (MIM) capacitor module with outer electrode extension
[patent_app_type] => utility
[patent_app_number] => 17/827648
[patent_app_country] => US
[patent_app_date] => 2022-05-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 2047
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 153
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17827648
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/827648 | Metal-insulator-metal (MIM) capacitor module with outer electrode extension | May 26, 2022 | Issued |
Array
(
[id] => 18812839
[patent_doc_number] => 20230387176
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-11-30
[patent_title] => SEMICONDUCTOR STRUCTURE OF BACKSIDE ILLUMINATION CMOS IMAGE SENSOR AND METHOD FOR FORMING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/824922
[patent_app_country] => US
[patent_app_date] => 2022-05-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7382
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 137
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17824922
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/824922 | SEMICONDUCTOR STRUCTURE OF BACKSIDE ILLUMINATION CMOS IMAGE SENSOR AND METHOD FOR FORMING THE SAME | May 25, 2022 | Pending |
Array
(
[id] => 18394752
[patent_doc_number] => 20230162973
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-05-25
[patent_title] => Gate Structure Fabrication Techniques for Reducing Gate Structure Warpage
[patent_app_type] => utility
[patent_app_number] => 17/825798
[patent_app_country] => US
[patent_app_date] => 2022-05-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14871
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 51
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17825798
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/825798 | Gate structure fabrication techniques for reducing gate structure warpage | May 25, 2022 | Issued |