Andre Pierre Louis

Array ( [id] => 420878 [patent_doc_number] => 07277841 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-10-02 [patent_title] => 'Method for adaptive sub-gridding for power/ground plane simulations' [patent_app_type] => utility [patent_app_number] => 10/361043 [patent_app_country] => US [patent_app_date] => 2003-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 4430 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/277/07277841.pdf [firstpage_image] =>[orig_patent_app_number] => 10361043 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7676526 [patent_doc_number] => 20040153301 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-05 [patent_title] => 'Integrated circuit development methodology' [patent_app_type] => new [patent_app_number] => 10/356917 [patent_app_country] => US [patent_app_date] => 2003-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7875 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20040153301.pdf [firstpage_image] =>[orig_patent_app_number] => 10356917 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 378589 [patent_doc_number] => 07313509 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-12-25 [patent_title] => 'Simulation method and apparatus, and computer-readable storage medium' [patent_app_type] => utility [patent_app_number] => 10/345338 [patent_app_country] => US [patent_app_date] => 2003-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 7023 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/313/07313509.pdf [firstpage_image] =>[orig_patent_app_number] => 10345338 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7327361 [patent_doc_number] => 20040138867 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-15 [patent_title] => 'System and method for modeling multi-tier distributed workload processes in complex systems' [patent_app_type] => new [patent_app_number] => 10/341507 [patent_app_country] => US [patent_app_date] => 2003-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4976 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20040138867.pdf [firstpage_image] =>[orig_patent_app_number] => 10341507 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 594290 [patent_doc_number] => 07454324 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-11-18 [patent_title] => 'Selection of initial states for formal verification' [patent_app_type] => utility [patent_app_number] => 10/340500 [patent_app_country] => US [patent_app_date] => 2003-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 40 [patent_no_of_words] => 20126 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 281 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/454/07454324.pdf [firstpage_image] =>[orig_patent_app_number] => 10340500 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 599353 [patent_doc_number] => 07440882 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-10-21 [patent_title] => 'Method and system for analyzing transaction level simulation data of an integrated circuit design' [patent_app_type] => utility [patent_app_number] => 10/335116 [patent_app_country] => US [patent_app_date] => 2002-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2834 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/440/07440882.pdf [firstpage_image] =>[orig_patent_app_number] => 10335116 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6798553 [patent_doc_number] => 20030177428 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-09-18 [patent_title] => 'Simulation method and apparatus for verifying logic circuit including processor' [patent_app_type] => new [patent_app_number] => 10/334003 [patent_app_country] => US [patent_app_date] => 2002-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3069 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0177/20030177428.pdf [firstpage_image] =>[orig_patent_app_number] => 10334003 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6762558 [patent_doc_number] => 20030125920 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-03 [patent_title] => 'LSI design verification apparatus, LSI design verification method, and LSI design verification program' [patent_app_type] => new [patent_app_number] => 10/330572 [patent_app_country] => US [patent_app_date] => 2002-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 39 [patent_no_of_words] => 20665 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0125/20030125920.pdf [firstpage_image] =>[orig_patent_app_number] => 10330572 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6762552 [patent_doc_number] => 20030125914 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-03 [patent_title] => 'System simulation using dynamic step size and iterative model' [patent_app_type] => new [patent_app_number] => 10/326693 [patent_app_country] => US [patent_app_date] => 2002-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3961 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0125/20030125914.pdf [firstpage_image] =>[orig_patent_app_number] => 10326693 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6665237 [patent_doc_number] => 20030204564 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-30 [patent_title] => 'Graphical modelling system' [patent_app_type] => new [patent_app_number] => 10/323940 [patent_app_country] => US [patent_app_date] => 2002-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4276 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0204/20030204564.pdf [firstpage_image] =>[orig_patent_app_number] => 10323940 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6866097 [patent_doc_number] => 20030191623 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-09 [patent_title] => 'Computer system capable of executing a remote operating system' [patent_app_type] => new [patent_app_number] => 10/313850 [patent_app_country] => US [patent_app_date] => 2002-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 17256 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0191/20030191623.pdf [firstpage_image] =>[orig_patent_app_number] => 10313850 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6707325 [patent_doc_number] => 20030154059 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-14 [patent_title] => 'Simulation apparatus and simulation method for a system having analog and digital elements' [patent_app_type] => new [patent_app_number] => 10/307828 [patent_app_country] => US [patent_app_date] => 2002-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5883 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0154/20030154059.pdf [firstpage_image] =>[orig_patent_app_number] => 10307828 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7596057 [patent_doc_number] => 07620525 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-11-17 [patent_title] => 'Method of generating CAD files and delivering CAD files to customers' [patent_app_type] => utility [patent_app_number] => 10/306135 [patent_app_country] => US [patent_app_date] => 2002-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 21 [patent_no_of_words] => 7176 [patent_no_of_claims] => 58 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/620/07620525.pdf [firstpage_image] =>[orig_patent_app_number] => 10306135 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 593623 [patent_doc_number] => 07457736 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-25 [patent_title] => 'Automated creation of metrology recipes' [patent_app_type] => utility [patent_app_number] => 10/301225 [patent_app_country] => US [patent_app_date] => 2002-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 5496 [patent_no_of_claims] => 66 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/457/07457736.pdf [firstpage_image] =>[orig_patent_app_number] => 10301225 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6844615 [patent_doc_number] => 20030149962 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-07 [patent_title] => 'Simulation of designs using programmable processors and electronically re-configurable logic arrays' [patent_app_type] => new [patent_app_number] => 10/301423 [patent_app_country] => US [patent_app_date] => 2002-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 18531 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0149/20030149962.pdf [firstpage_image] =>[orig_patent_app_number] => 10301423 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 381016 [patent_doc_number] => 07310594 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-12-18 [patent_title] => 'Method and system for designing a multiprocessor' [patent_app_type] => utility [patent_app_number] => 10/295687 [patent_app_country] => US [patent_app_date] => 2002-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 6141 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/310/07310594.pdf [firstpage_image] =>[orig_patent_app_number] => 10295687 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6684594 [patent_doc_number] => 20030120458 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-26 [patent_title] => 'Patient data mining' [patent_app_type] => new [patent_app_number] => 10/287055 [patent_app_country] => US [patent_app_date] => 2002-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4833 [patent_no_of_claims] => 54 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 15 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0120/20030120458.pdf [firstpage_image] =>[orig_patent_app_number] => 10287055 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 106685 [patent_doc_number] => 07725301 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-25 [patent_title] => 'System and method for estimating multi-phase fluid rates in a subterranean well' [patent_app_type] => utility [patent_app_number] => 10/287744 [patent_app_country] => US [patent_app_date] => 2002-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3943 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/725/07725301.pdf [firstpage_image] =>[orig_patent_app_number] => 10287744 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6702677 [patent_doc_number] => 20030225557 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-12-04 [patent_title] => 'Method and system for realizing a logic model design' [patent_app_type] => new [patent_app_number] => 10/284294 [patent_app_country] => US [patent_app_date] => 2002-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4863 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0225/20030225557.pdf [firstpage_image] =>[orig_patent_app_number] => 10284294 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7383835 [patent_doc_number] => 20040082230 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-29 [patent_title] => 'Analyzing interconnect structures' [patent_app_type] => new [patent_app_number] => 10/281857 [patent_app_country] => US [patent_app_date] => 2002-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2592 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0082/20040082230.pdf [firstpage_image] =>[orig_patent_app_number] => 10281857 [rel_patent_id] =>[rel_patent_doc_number] =>)