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Andre Pierre Louis

Examiner (ID: 3676)

Most Active Art Unit
2123
Art Unit(s)
2146, 2127, 2123, 2187
Total Applications
902
Issued Applications
615
Pending Applications
62
Abandoned Applications
234

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7175055 [patent_doc_number] => 20040078674 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-22 [patent_title] => 'Methods and apparatus for generating functional test programs by traversing a finite state model of an instruction set architecture' [patent_app_type] => new [patent_app_number] => 10/116221 [patent_app_country] => US [patent_app_date] => 2002-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10588 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0078/20040078674.pdf [firstpage_image] =>[orig_patent_app_number] => 10116221 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/116221
Methods and apparatus for generating functional test programs by traversing a finite state model of an instruction set architecture Apr 3, 2002 Abandoned
Array ( [id] => 6751524 [patent_doc_number] => 20030046045 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-06 [patent_title] => 'Method and apparatus for analysing and modeling of analog systems' [patent_app_type] => new [patent_app_number] => 10/100402 [patent_app_country] => US [patent_app_date] => 2002-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 7007 [patent_no_of_claims] => 56 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20030046045.pdf [firstpage_image] =>[orig_patent_app_number] => 10100402 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/100402
Method and apparatus for analysing and modeling of analog systems Mar 17, 2002 Abandoned
Array ( [id] => 6560278 [patent_doc_number] => 20020111783 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-15 [patent_title] => 'Simulation, measurement and/or control system and method with coordinated timing' [patent_app_type] => new [patent_app_number] => 10/053521 [patent_app_country] => US [patent_app_date] => 2002-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9355 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0111/20020111783.pdf [firstpage_image] =>[orig_patent_app_number] => 10053521 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/053521
Simulation, measurement and/or control system and method with coordinated timing Jan 17, 2002 Issued
Array ( [id] => 712557 [patent_doc_number] => 07062423 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-06-13 [patent_title] => 'Method and apparatus for testing a system on a chip (SOC) integrated circuit comprising a hard disk controller and read channel' [patent_app_type] => utility [patent_app_number] => 10/042548 [patent_app_country] => US [patent_app_date] => 2002-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3074 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/062/07062423.pdf [firstpage_image] =>[orig_patent_app_number] => 10042548 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/042548
Method and apparatus for testing a system on a chip (SOC) integrated circuit comprising a hard disk controller and read channel Jan 8, 2002 Issued
Array ( [id] => 6857331 [patent_doc_number] => 20030130832 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-10 [patent_title] => 'Virtual networking system and method in a processing system' [patent_app_type] => new [patent_app_number] => 10/037191 [patent_app_country] => US [patent_app_date] => 2002-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 16527 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0130/20030130832.pdf [firstpage_image] =>[orig_patent_app_number] => 10037191 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/037191
Virtual networking system and method in a processing system Jan 3, 2002 Abandoned
Array ( [id] => 6419350 [patent_doc_number] => 20020183928 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-05 [patent_title] => 'Model-supported allocation of vehicles to traffic lanes' [patent_app_type] => new [patent_app_number] => 09/980146 [patent_app_country] => US [patent_app_date] => 2002-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2248 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0183/20020183928.pdf [firstpage_image] =>[orig_patent_app_number] => 09980146 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/980146
Model-supported allocation of vehicles to traffic lanes Mar 7, 2001 Issued
Array ( [id] => 7361368 [patent_doc_number] => 20040049772 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-11 [patent_title] => 'Method for configuring an electrical installation and corresponding configuration device' [patent_app_type] => new [patent_app_number] => 10/130216 [patent_app_country] => US [patent_app_date] => 2002-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5847 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0049/20040049772.pdf [firstpage_image] =>[orig_patent_app_number] => 10130216 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/130216
Method for configuring an electrical installation and corresponding configuration device Mar 1, 2001 Issued
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