
Andres F. Munoz
Examiner (ID: 16760, Phone: (571)270-3346 , Office: P/2894 )
| Most Active Art Unit | 2894 |
| Art Unit(s) | 2818, 2897, 2894 |
| Total Applications | 939 |
| Issued Applications | 698 |
| Pending Applications | 97 |
| Abandoned Applications | 177 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 19054727
[patent_doc_number] => 20240096696
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-03-21
[patent_title] => STRUCTURES WITH CONVEX CAVITY BOTTOMS
[patent_app_type] => utility
[patent_app_number] => 18/155926
[patent_app_country] => US
[patent_app_date] => 2023-01-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5885
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 64
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18155926
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/155926 | STRUCTURES WITH CONVEX CAVITY BOTTOMS | Jan 17, 2023 | Pending |
Array
(
[id] => 18868031
[patent_doc_number] => 20230422468
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-12-28
[patent_title] => METHOD FOR PREPARING SEMICONDUCTOR STRUCTURE, SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR MEMORY
[patent_app_type] => utility
[patent_app_number] => 18/155114
[patent_app_country] => US
[patent_app_date] => 2023-01-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11989
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 135
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18155114
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/155114 | METHOD FOR PREPARING SEMICONDUCTOR STRUCTURE, SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR MEMORY | Jan 16, 2023 | Pending |
Array
(
[id] => 19024911
[patent_doc_number] => 20240081082
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-03-07
[patent_title] => SEMICONDUCTOR DEVICE INCLUDING BARRIER DIELECTRIC LAYER INCLUDING FERROELECTRIC MATERIAL
[patent_app_type] => utility
[patent_app_number] => 18/097493
[patent_app_country] => US
[patent_app_date] => 2023-01-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 20737
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -44
[patent_words_short_claim] => 73
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18097493
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/097493 | SEMICONDUCTOR DEVICE INCLUDING BARRIER DIELECTRIC LAYER INCLUDING FERROELECTRIC MATERIAL | Jan 16, 2023 | Pending |
Array
(
[id] => 18907846
[patent_doc_number] => 20240023331
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-01-18
[patent_title] => SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD OF THE SEMICONDUCTOR MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/097903
[patent_app_country] => US
[patent_app_date] => 2023-01-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6601
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 24
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18097903
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/097903 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD OF THE SEMICONDUCTOR MEMORY DEVICE | Jan 16, 2023 | Pending |
Array
(
[id] => 19054949
[patent_doc_number] => 20240096918
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-03-21
[patent_title] => IMAGE SENSOR PACKAGING AND METHODS FOR FORMING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/155491
[patent_app_country] => US
[patent_app_date] => 2023-01-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11040
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18155491
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/155491 | IMAGE SENSOR PACKAGING AND METHODS FOR FORMING THE SAME | Jan 16, 2023 | Pending |
Array
(
[id] => 18533366
[patent_doc_number] => 20230238442
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-07-27
[patent_title] => SEMICONDUCTOR DEVICE WITH METAL NITRIDE LAYER AND A METHOD OF MANUFACTURING THEREOF
[patent_app_type] => utility
[patent_app_number] => 18/097656
[patent_app_country] => US
[patent_app_date] => 2023-01-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7560
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18097656
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/097656 | SEMICONDUCTOR DEVICE WITH METAL NITRIDE LAYER AND A METHOD OF MANUFACTURING THEREOF | Jan 16, 2023 | Pending |
Array
(
[id] => 18680108
[patent_doc_number] => 20230317766
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-10-05
[patent_title] => DISPLAY DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/155592
[patent_app_country] => US
[patent_app_date] => 2023-01-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 17494
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 55
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18155592
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/155592 | DISPLAY DEVICE | Jan 16, 2023 | Pending |
Array
(
[id] => 18907846
[patent_doc_number] => 20240023331
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-01-18
[patent_title] => SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD OF THE SEMICONDUCTOR MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/097903
[patent_app_country] => US
[patent_app_date] => 2023-01-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6601
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 24
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18097903
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/097903 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD OF THE SEMICONDUCTOR MEMORY DEVICE | Jan 16, 2023 | Pending |
Array
(
[id] => 18540916
[patent_doc_number] => 20230246027
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-08-03
[patent_title] => VERTICAL FIN-BASED FIELD EFFECT TRANSISTOR (FINFET) WITH NEUTRALIZED FIN TIPS
[patent_app_type] => utility
[patent_app_number] => 18/097693
[patent_app_country] => US
[patent_app_date] => 2023-01-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9060
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 152
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18097693
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/097693 | Vertical fin-based field effect transistor (FinFET) with neutralized fin tips | Jan 16, 2023 | Issued |
Array
(
[id] => 19024911
[patent_doc_number] => 20240081082
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-03-07
[patent_title] => SEMICONDUCTOR DEVICE INCLUDING BARRIER DIELECTRIC LAYER INCLUDING FERROELECTRIC MATERIAL
[patent_app_type] => utility
[patent_app_number] => 18/097493
[patent_app_country] => US
[patent_app_date] => 2023-01-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 20737
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -44
[patent_words_short_claim] => 73
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18097493
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/097493 | SEMICONDUCTOR DEVICE INCLUDING BARRIER DIELECTRIC LAYER INCLUDING FERROELECTRIC MATERIAL | Jan 16, 2023 | Pending |
Array
(
[id] => 18540916
[patent_doc_number] => 20230246027
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-08-03
[patent_title] => VERTICAL FIN-BASED FIELD EFFECT TRANSISTOR (FINFET) WITH NEUTRALIZED FIN TIPS
[patent_app_type] => utility
[patent_app_number] => 18/097693
[patent_app_country] => US
[patent_app_date] => 2023-01-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9060
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 152
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18097693
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/097693 | Vertical fin-based field effect transistor (FinFET) with neutralized fin tips | Jan 16, 2023 | Issued |
Array
(
[id] => 19146425
[patent_doc_number] => 20240145455
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-05-02
[patent_title] => ELECTRONIC PACKAGE AND MANUFACTURING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 18/155337
[patent_app_country] => US
[patent_app_date] => 2023-01-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3868
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18155337
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/155337 | ELECTRONIC PACKAGE AND MANUFACTURING METHOD THEREOF | Jan 16, 2023 | Pending |
Array
(
[id] => 18680108
[patent_doc_number] => 20230317766
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-10-05
[patent_title] => DISPLAY DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/155592
[patent_app_country] => US
[patent_app_date] => 2023-01-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 17494
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 55
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18155592
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/155592 | DISPLAY DEVICE | Jan 16, 2023 | Pending |
Array
(
[id] => 19321647
[patent_doc_number] => 20240243194
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-07-18
[patent_title] => HIGH ELECTRON MOBILITY TRANSISTOR STRUCTURE AND FABRICATION METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 18/098079
[patent_app_country] => US
[patent_app_date] => 2023-01-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6915
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18098079
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/098079 | HIGH ELECTRON MOBILITY TRANSISTOR STRUCTURE AND FABRICATION METHOD THEREOF | Jan 16, 2023 | Issued |
Array
(
[id] => 18868031
[patent_doc_number] => 20230422468
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-12-28
[patent_title] => METHOD FOR PREPARING SEMICONDUCTOR STRUCTURE, SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR MEMORY
[patent_app_type] => utility
[patent_app_number] => 18/155114
[patent_app_country] => US
[patent_app_date] => 2023-01-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11989
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 135
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18155114
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/155114 | METHOD FOR PREPARING SEMICONDUCTOR STRUCTURE, SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR MEMORY | Jan 16, 2023 | Pending |
Array
(
[id] => 20347670
[patent_doc_number] => 12471408
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-11-11
[patent_title] => Semiconductor structure and method of manufacturing the same
[patent_app_type] => utility
[patent_app_number] => 18/152172
[patent_app_country] => US
[patent_app_date] => 2023-01-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 2199
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 51
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18152172
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/152172 | Semiconductor structure and method of manufacturing the same | Jan 9, 2023 | Issued |
Array
(
[id] => 18366464
[patent_doc_number] => 20230148055
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-05-11
[patent_title] => THREE-DIMENSIONAL MEMORY AND ITS FABRICATION METHOD
[patent_app_type] => utility
[patent_app_number] => 18/089463
[patent_app_country] => US
[patent_app_date] => 2022-12-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5219
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18089463
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/089463 | THREE-DIMENSIONAL MEMORY AND ITS FABRICATION METHOD | Dec 26, 2022 | Pending |
Array
(
[id] => 19206212
[patent_doc_number] => 20240178111
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-05-30
[patent_title] => SEMICONDUCTOR DEVICE WITH ATTACHED BATTERY AND METHOD THEREFOR
[patent_app_type] => utility
[patent_app_number] => 18/059465
[patent_app_country] => US
[patent_app_date] => 2022-11-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4903
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 126
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18059465
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/059465 | Semiconductor device with attached battery and method therefor | Nov 28, 2022 | Issued |
Array
(
[id] => 18283527
[patent_doc_number] => 20230098999
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-03-30
[patent_title] => SEMICONDUCTOR STRUCTURE
[patent_app_type] => utility
[patent_app_number] => 17/989528
[patent_app_country] => US
[patent_app_date] => 2022-11-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6961
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17989528
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/989528 | Semiconductor structure | Nov 16, 2022 | Issued |
Array
(
[id] => 19229793
[patent_doc_number] => 12009437
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-06-11
[patent_title] => Method for manufacturing a semiconductor structure having group III-V device on group IV substrate and contacts with liner stacks
[patent_app_type] => utility
[patent_app_number] => 17/977503
[patent_app_country] => US
[patent_app_date] => 2022-10-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 7886
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 128
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17977503
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/977503 | Method for manufacturing a semiconductor structure having group III-V device on group IV substrate and contacts with liner stacks | Oct 30, 2022 | Issued |