Andrew Howard Hirshfeld

Array ( [id] => 20416903 [patent_doc_number] => 12500198 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-16 [patent_title] => Quad flat no-lead (QFN) package with tie bars and direct contact interconnect build-up structure and method for making the same [patent_app_type] => utility [patent_app_number] => 19/064511 [patent_app_country] => US [patent_app_date] => 2025-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 30 [patent_no_of_words] => 8065 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19064511 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20283911 [patent_doc_number] => 20250309153 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-02 [patent_title] => Apparatus and Method for Mitigating Crosstalk in an Advanced Package [patent_app_type] => utility [patent_app_number] => 18/754504 [patent_app_country] => US [patent_app_date] => 2024-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18754504 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20455980 [patent_doc_number] => 12519042 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-06 [patent_title] => Methods for manufacturing a semiconductor package and a semiconductor module [patent_app_type] => utility [patent_app_number] => 18/629215 [patent_app_country] => US [patent_app_date] => 2024-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 59 [patent_no_of_words] => 7813 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18629215 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20441553 [patent_doc_number] => 12512395 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-30 [patent_title] => Chip packaging method and chip package unit [patent_app_type] => utility [patent_app_number] => 18/616275 [patent_app_country] => US [patent_app_date] => 2024-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 17 [patent_no_of_words] => 0 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18616275 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20509170 [patent_doc_number] => 12543462 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-03 [patent_title] => Display substrate and display device [patent_app_type] => utility [patent_app_number] => 18/615509 [patent_app_country] => US [patent_app_date] => 2024-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 26 [patent_no_of_words] => 27087 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18615509 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19269474 [patent_doc_number] => 20240213178 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => SEMICONDUCTOR DEVICE HAVING TAPERED METAL COATED SIDEWALLS [patent_app_type] => utility [patent_app_number] => 18/595905 [patent_app_country] => US [patent_app_date] => 2024-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7247 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18595905 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20496933 [patent_doc_number] => 12538827 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-27 [patent_title] => Semiconductor structure [patent_app_type] => utility [patent_app_number] => 18/592523 [patent_app_country] => US [patent_app_date] => 2024-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 2305 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18592523 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20583178 [patent_doc_number] => 12575441 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-10 [patent_title] => System and method for manufacturing a semiconductor package structure [patent_app_type] => utility [patent_app_number] => 18/427769 [patent_app_country] => US [patent_app_date] => 2024-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 2311 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18427769 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19176197 [patent_doc_number] => 20240162171 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-16 [patent_title] => METHOD FOR FABRICATING DEVICE DIE [patent_app_type] => utility [patent_app_number] => 18/418318 [patent_app_country] => US [patent_app_date] => 2024-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12347 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18418318 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20111591 [patent_doc_number] => 12362327 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-15 [patent_title] => Method of forming packages of stacked chips [patent_app_type] => utility [patent_app_number] => 18/413020 [patent_app_country] => US [patent_app_date] => 2024-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 1230 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 292 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18413020 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20098211 [patent_doc_number] => 20250228147 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-10 [patent_title] => MEMORY STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/409163 [patent_app_country] => US [patent_app_date] => 2024-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2414 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18409163 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20098209 [patent_doc_number] => 20250228145 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-10 [patent_title] => RESISTIVE RANDOM-ACCESS MEMORY (RRAM) STRUCTURES AND METHODS OF FORMING SAME [patent_app_type] => utility [patent_app_number] => 18/409126 [patent_app_country] => US [patent_app_date] => 2024-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3302 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18409126 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19239521 [patent_doc_number] => 20240196717 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-13 [patent_title] => Pixel configurations for high resolution OVJP printed OLED displays [patent_app_type] => utility [patent_app_number] => 18/405312 [patent_app_country] => US [patent_app_date] => 2024-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10044 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18405312 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20088964 [patent_doc_number] => 20250218900 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-03 [patent_title] => THROUGH SUBSTRATE VIA WITH SPACED SHALLOW TRENCH ISOLATION [patent_app_type] => utility [patent_app_number] => 18/400104 [patent_app_country] => US [patent_app_date] => 2023-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18400104 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19366071 [patent_doc_number] => 20240268105 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-08 [patent_title] => SEMICONDUCTOR DEVICE INCLUDING A PERIPHERAL CIRCUIT DEVICE [patent_app_type] => utility [patent_app_number] => 18/391804 [patent_app_country] => US [patent_app_date] => 2023-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13684 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18391804 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20416902 [patent_doc_number] => 12500197 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-16 [patent_title] => Encapsulant-defined land grid array (LGA) package and method for making the same [patent_app_type] => utility [patent_app_number] => 18/389741 [patent_app_country] => US [patent_app_date] => 2023-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 35 [patent_no_of_words] => 5610 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18389741 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20132241 [patent_doc_number] => 12374559 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-29 [patent_title] => Double-sided partial molded SiP module [patent_app_type] => utility [patent_app_number] => 18/543992 [patent_app_country] => US [patent_app_date] => 2023-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 26 [patent_no_of_words] => 0 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18543992 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19269701 [patent_doc_number] => 20240213406 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => MICRO LED STRUCTURE AND MICRO LED PANEL [patent_app_type] => utility [patent_app_number] => 18/542752 [patent_app_country] => US [patent_app_date] => 2023-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4801 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18542752 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19517875 [patent_doc_number] => 20240349561 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-17 [patent_title] => Display Panel [patent_app_type] => utility [patent_app_number] => 18/542683 [patent_app_country] => US [patent_app_date] => 2023-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5183 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18542683 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19288252 [patent_doc_number] => 20240224735 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 18/528467 [patent_app_country] => US [patent_app_date] => 2023-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7978 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18528467 [rel_patent_id] =>[rel_patent_doc_number] =>)