Search

Andrew J. Fischer

Supervisory Patent Examiner (ID: 575, Phone: (571)272-6779 , Office: P/3992 )

Most Active Art Unit
3627
Art Unit(s)
3611, 3627, 3992, 2167, 3621, 3619
Total Applications
435
Issued Applications
228
Pending Applications
84
Abandoned Applications
123

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19508030 [patent_doc_number] => 12119462 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-15 [patent_title] => Sensing device for detecting analytes in batteries [patent_app_type] => utility [patent_app_number] => 17/182082 [patent_app_country] => US [patent_app_date] => 2021-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 33 [patent_no_of_words] => 14381 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17182082 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/182082
Sensing device for detecting analytes in batteries Feb 21, 2021 Issued
Array ( [id] => 17347696 [patent_doc_number] => 20220014027 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-13 [patent_title] => APPARATUS FOR IMPROVING CELL BALANCING AND CELL FAILURE DETECTION [patent_app_type] => utility [patent_app_number] => 17/181968 [patent_app_country] => US [patent_app_date] => 2021-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7045 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17181968 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/181968
APPARATUS FOR IMPROVING CELL BALANCING AND CELL FAILURE DETECTION Feb 21, 2021 Abandoned
Array ( [id] => 17024428 [patent_doc_number] => 20210248300 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-12 [patent_title] => Systems and Methods for Improving Design Performance Through Placement of Functional and Spare Cells by Leveraging LDE Effect [patent_app_type] => utility [patent_app_number] => 17/179690 [patent_app_country] => US [patent_app_date] => 2021-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6541 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17179690 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/179690
Systems and methods for improving design performance through placement of functional and spare cells by leveraging LDE effect Feb 18, 2021 Issued
Array ( [id] => 17651740 [patent_doc_number] => 11354470 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-06-07 [patent_title] => System and method for device placement [patent_app_type] => utility [patent_app_number] => 17/173440 [patent_app_country] => US [patent_app_date] => 2021-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5952 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17173440 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/173440
System and method for device placement Feb 10, 2021 Issued
Array ( [id] => 17515902 [patent_doc_number] => 11295057 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-04-05 [patent_title] => Continuous and discrete corner regularization in multi-PVT timing prediction [patent_app_type] => utility [patent_app_number] => 17/172200 [patent_app_country] => US [patent_app_date] => 2021-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10636 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17172200 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/172200
Continuous and discrete corner regularization in multi-PVT timing prediction Feb 9, 2021 Issued
Array ( [id] => 18243082 [patent_doc_number] => 20230075393 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-09 [patent_title] => APPARATUS, SYSTEMS AND METHODS FOR LOAD-ADAPTIVE 3D WIRELESS CHARGING [patent_app_type] => utility [patent_app_number] => 17/800316 [patent_app_country] => US [patent_app_date] => 2021-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14280 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -35 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17800316 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/800316
APPARATUS, SYSTEMS AND METHODS FOR LOAD-ADAPTIVE 3D WIRELESS CHARGING Feb 4, 2021 Pending
Array ( [id] => 16872475 [patent_doc_number] => 20210165942 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-03 [patent_title] => DETECTING OUT-OF-BOUNDS VIOLATIONS IN A HARDWARE DESIGN USING FORMAL VERIFICATION [patent_app_type] => utility [patent_app_number] => 17/168945 [patent_app_country] => US [patent_app_date] => 2021-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13738 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 268 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17168945 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/168945
Detecting out-of-bounds violations in a hardware design using formal verification Feb 4, 2021 Issued
Array ( [id] => 17778971 [patent_doc_number] => 20220245321 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-04 [patent_title] => APPARATUS AND METHOD FOR GENERATING A PARAMETERIZED WAVEGUIDE OPTICAL ELEMENTS [patent_app_type] => utility [patent_app_number] => 17/162912 [patent_app_country] => US [patent_app_date] => 2021-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5628 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17162912 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/162912
Apparatus and method for generating a parameterized waveguide optical elements Jan 28, 2021 Issued
Array ( [id] => 17589839 [patent_doc_number] => 11328112 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-05-10 [patent_title] => Timing-aware testing [patent_app_type] => utility [patent_app_number] => 17/160192 [patent_app_country] => US [patent_app_date] => 2021-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4384 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17160192 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/160192
Timing-aware testing Jan 26, 2021 Issued
Array ( [id] => 17352454 [patent_doc_number] => 11227093 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-18 [patent_title] => Method and system of forming semiconductor device [patent_app_type] => utility [patent_app_number] => 17/157765 [patent_app_country] => US [patent_app_date] => 2021-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6980 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17157765 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/157765
Method and system of forming semiconductor device Jan 24, 2021 Issued
Array ( [id] => 18703618 [patent_doc_number] => 11790132 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-17 [patent_title] => Calculation method of eddy current loss in magnetic materials based on magnetic-inductance [patent_app_type] => utility [patent_app_number] => 17/612942 [patent_app_country] => US [patent_app_date] => 2021-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3143 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 353 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17612942 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/612942
Calculation method of eddy current loss in magnetic materials based on magnetic-inductance Jan 21, 2021 Issued
Array ( [id] => 19062099 [patent_doc_number] => 11941335 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-03-26 [patent_title] => Providing concise data for analyzing checker completeness [patent_app_type] => utility [patent_app_number] => 17/152289 [patent_app_country] => US [patent_app_date] => 2021-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 10210 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17152289 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/152289
Providing concise data for analyzing checker completeness Jan 18, 2021 Issued
Array ( [id] => 17309332 [patent_doc_number] => 11210448 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-12-28 [patent_title] => Mitigating timing yield loss due to high-sigma rare-event process variation [patent_app_type] => utility [patent_app_number] => 17/150980 [patent_app_country] => US [patent_app_date] => 2021-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5306 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17150980 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/150980
Mitigating timing yield loss due to high-sigma rare-event process variation Jan 14, 2021 Issued
Array ( [id] => 17877638 [patent_doc_number] => 11449654 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-09-20 [patent_title] => System, method, and computer program product for augmented reality circuit design [patent_app_type] => utility [patent_app_number] => 17/146019 [patent_app_country] => US [patent_app_date] => 2021-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 11100 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17146019 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/146019
System, method, and computer program product for augmented reality circuit design Jan 10, 2021 Issued
Array ( [id] => 17469402 [patent_doc_number] => 11275881 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-03-15 [patent_title] => System, method, and computer program product for genetic routing in an electronic circuit design [patent_app_type] => utility [patent_app_number] => 17/140510 [patent_app_country] => US [patent_app_date] => 2021-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 8237 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17140510 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/140510
System, method, and computer program product for genetic routing in an electronic circuit design Jan 3, 2021 Issued
Array ( [id] => 17802359 [patent_doc_number] => 11416660 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-08-16 [patent_title] => Automatic placement of analog design components with virtual grouping [patent_app_type] => utility [patent_app_number] => 17/138833 [patent_app_country] => US [patent_app_date] => 2020-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 6025 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17138833 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/138833
Automatic placement of analog design components with virtual grouping Dec 29, 2020 Issued
Array ( [id] => 17492522 [patent_doc_number] => 11281827 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-03-22 [patent_title] => Optimization of parameters for synthesis of a topology using a discriminant function module [patent_app_type] => utility [patent_app_number] => 17/134380 [patent_app_country] => US [patent_app_date] => 2020-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5506 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17134380 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/134380
Optimization of parameters for synthesis of a topology using a discriminant function module Dec 25, 2020 Issued
Array ( [id] => 17151622 [patent_doc_number] => 11144700 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-10-12 [patent_title] => Grouping nets to facilitate repeater insertion [patent_app_type] => utility [patent_app_number] => 17/125522 [patent_app_country] => US [patent_app_date] => 2020-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 5929 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17125522 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/125522
Grouping nets to facilitate repeater insertion Dec 16, 2020 Issued
Array ( [id] => 17786815 [patent_doc_number] => 11409940 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-09 [patent_title] => Virtual to real waveform emulator [patent_app_type] => utility [patent_app_number] => 17/124484 [patent_app_country] => US [patent_app_date] => 2020-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 7710 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17124484 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/124484
Virtual to real waveform emulator Dec 15, 2020 Issued
Array ( [id] => 17645866 [patent_doc_number] => 20220173605 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-02 [patent_title] => CONTROLLING CHARGING OF COMPUTING DEVICE THROUGH PORTS CONNECTED TO EXTERNAL DEVICES [patent_app_type] => utility [patent_app_number] => 17/106410 [patent_app_country] => US [patent_app_date] => 2020-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4951 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17106410 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/106410
Controlling charging of computing device through ports connected to external devices Nov 29, 2020 Issued
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