Andrew J Oyer

Array ( [id] => 3757279 [patent_doc_number] => 05721171 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-24 [patent_title] => 'Method for forming controllable surface enhanced three dimensional objects' [patent_app_type] => 1 [patent_app_number] => 8/609077 [patent_app_country] => US [patent_app_date] => 1996-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 2220 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/721/05721171.pdf [firstpage_image] =>[orig_patent_app_number] => 609077 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3773855 [patent_doc_number] => 05817547 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-06 [patent_title] => 'Method for fabricating a metal oxide semiconductor field effect transistor having a multi-layered gate electrode' [patent_app_type] => 1 [patent_app_number] => 8/607641 [patent_app_country] => US [patent_app_date] => 1996-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 15 [patent_no_of_words] => 3879 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/817/05817547.pdf [firstpage_image] =>[orig_patent_app_number] => 607641 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3993986 [patent_doc_number] => 05918109 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-29 [patent_title] => 'Method for making optical semiconductor element' [patent_app_type] => 1 [patent_app_number] => 8/605673 [patent_app_country] => US [patent_app_date] => 1996-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 24 [patent_no_of_words] => 3909 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/918/05918109.pdf [firstpage_image] =>[orig_patent_app_number] => 605673 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3943148 [patent_doc_number] => 05976905 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-02 [patent_title] => 'Method of manufacturing VCSEL arrays using vapor phase epitaxy to achieve uniform device-to-device operating characteristics' [patent_app_type] => 1 [patent_app_number] => 8/602609 [patent_app_country] => US [patent_app_date] => 1996-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3610 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/976/05976905.pdf [firstpage_image] =>[orig_patent_app_number] => 602609 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3647646 [patent_doc_number] => 05639676 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-06-17 [patent_title] => 'Trenched DMOS transistor fabrication having thick termination region oxide' [patent_app_type] => 1 [patent_app_number] => 8/603047 [patent_app_country] => US [patent_app_date] => 1996-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 11 [patent_no_of_words] => 2281 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/639/05639676.pdf [firstpage_image] =>[orig_patent_app_number] => 603047 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3925696 [patent_doc_number] => 05877035 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-02 [patent_title] => 'Analyzing method and apparatus for minute foreign substances, and manufacturing methods for manufacturing semiconductor device and liquid crystal display device using the same' [patent_app_type] => 1 [patent_app_number] => 8/600141 [patent_app_country] => US [patent_app_date] => 1996-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 15638 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/877/05877035.pdf [firstpage_image] =>[orig_patent_app_number] => 600141 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3884981 [patent_doc_number] => 05723348 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-03 [patent_title] => 'Method of making a light-emitting device' [patent_app_type] => 1 [patent_app_number] => 8/598623 [patent_app_country] => US [patent_app_date] => 1996-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 3170 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/723/05723348.pdf [firstpage_image] =>[orig_patent_app_number] => 598623 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3690621 [patent_doc_number] => 05604134 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-18 [patent_title] => 'Particle monitoring method for plasma reactors with moving gas distribution housings' [patent_app_type] => 1 [patent_app_number] => 8/597493 [patent_app_country] => US [patent_app_date] => 1996-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2066 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/604/05604134.pdf [firstpage_image] =>[orig_patent_app_number] => 597493 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3632857 [patent_doc_number] => 05610090 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-03-11 [patent_title] => 'Method of making a FET having a recessed gate structure' [patent_app_type] => 1 [patent_app_number] => 8/589569 [patent_app_country] => US [patent_app_date] => 1996-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 21 [patent_no_of_words] => 3876 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/610/05610090.pdf [firstpage_image] =>[orig_patent_app_number] => 589569 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4058630 [patent_doc_number] => 05913111 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-15 [patent_title] => 'Method of manufacturing an insulaed gate transistor' [patent_app_type] => 1 [patent_app_number] => 8/587661 [patent_app_country] => US [patent_app_date] => 1996-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 30 [patent_no_of_words] => 5408 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/913/05913111.pdf [firstpage_image] =>[orig_patent_app_number] => 587661 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3651271 [patent_doc_number] => 05622565 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-22 [patent_title] => 'Reduction of contaminant buildup in semiconductor apparatus' [patent_app_type] => 1 [patent_app_number] => 8/585980 [patent_app_country] => US [patent_app_date] => 1996-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 5564 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/622/05622565.pdf [firstpage_image] =>[orig_patent_app_number] => 585980 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3969434 [patent_doc_number] => 05904556 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-18 [patent_title] => 'Method for making semiconductor integrated circuit device having interconnection structure using tungsten film' [patent_app_type] => 1 [patent_app_number] => 8/584065 [patent_app_country] => US [patent_app_date] => 1996-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 6308 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/904/05904556.pdf [firstpage_image] =>[orig_patent_app_number] => 584065 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3832236 [patent_doc_number] => 05712204 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-27 [patent_title] => 'Method of making a semiconductor device having reduced junction capacitance between the source and drain regions and the substrate' [patent_app_type] => 1 [patent_app_number] => 8/575475 [patent_app_country] => US [patent_app_date] => 1995-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 18 [patent_no_of_words] => 3800 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/712/05712204.pdf [firstpage_image] =>[orig_patent_app_number] => 575475 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4011800 [patent_doc_number] => 05879962 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-09 [patent_title] => 'III-V/II-VI Semiconductor interface fabrication method' [patent_app_type] => 1 [patent_app_number] => 8/571607 [patent_app_country] => US [patent_app_date] => 1995-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 8307 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/879/05879962.pdf [firstpage_image] =>[orig_patent_app_number] => 571607 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3768831 [patent_doc_number] => 05733812 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-31 [patent_title] => 'Semiconductor device with a field-effect transistor having a lower resistance impurity diffusion layer, and method of manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 8/571131 [patent_app_country] => US [patent_app_date] => 1995-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 70 [patent_no_of_words] => 13477 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/733/05733812.pdf [firstpage_image] =>[orig_patent_app_number] => 571131 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3825653 [patent_doc_number] => 05783474 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-21 [patent_title] => 'Reduced mask process for manufacture of MOS gated devices using dopant-enhanced-oxidation of semiconductor' [patent_app_type] => 1 [patent_app_number] => 8/570517 [patent_app_country] => US [patent_app_date] => 1995-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 26 [patent_no_of_words] => 4948 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/783/05783474.pdf [firstpage_image] =>[orig_patent_app_number] => 570517 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3601465 [patent_doc_number] => 05578511 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-26 [patent_title] => 'Method of making signal charge transfer devices' [patent_app_type] => 1 [patent_app_number] => 8/569317 [patent_app_country] => US [patent_app_date] => 1995-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 15 [patent_no_of_words] => 3682 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 25 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/578/05578511.pdf [firstpage_image] =>[orig_patent_app_number] => 569317 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3740276 [patent_doc_number] => 05786231 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-28 [patent_title] => 'Screening method for selecting semiconductor substrates having defects below a predetermined level in an oxide layer' [patent_app_type] => 1 [patent_app_number] => 8/567679 [patent_app_country] => US [patent_app_date] => 1995-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5306 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/786/05786231.pdf [firstpage_image] =>[orig_patent_app_number] => 567679 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3665430 [patent_doc_number] => 05599726 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-04 [patent_title] => 'Method of making a conductive spacer lightly doped drain (LDD) for hot carrier effect (HCE) control' [patent_app_type] => 1 [patent_app_number] => 8/567017 [patent_app_country] => US [patent_app_date] => 1995-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 4504 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/599/05599726.pdf [firstpage_image] =>[orig_patent_app_number] => 567017 [rel_patent_id] =>[rel_patent_doc_number] =>)