Andrew J Oyer
Examiner (ID: 2471, Phone: (571)270-0347 , Office: P/1767 )
Most Active Art Unit | 1767 |
Art Unit(s) | 1767 |
Total Applications | 638 |
Issued Applications | 430 |
Pending Applications | 78 |
Abandoned Applications | 130 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 4139351
[patent_doc_number] => 06121634
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-09-19
[patent_title] => 'Nitride semiconductor light emitting device and its manufacturing method'
[patent_app_type] => 1
[patent_app_number] => 9/027490
[patent_app_country] => US
[patent_app_date] => 1998-02-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
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[patent_no_of_words] => 10387
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[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/121/06121634.pdf
[firstpage_image] =>[orig_patent_app_number] => 027490
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/027490 | Nitride semiconductor light emitting device and its manufacturing method | Feb 19, 1998 | Issued |
Array
(
[id] => 4236212
[patent_doc_number] => 06143660
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-11-07
[patent_title] => 'Method of producing a contact between a metallizing layer and a semiconductor material'
[patent_app_type] => 1
[patent_app_number] => 9/023720
[patent_app_country] => US
[patent_app_date] => 1998-02-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/143/06143660.pdf
[firstpage_image] =>[orig_patent_app_number] => 023720
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/023720 | Method of producing a contact between a metallizing layer and a semiconductor material | Feb 12, 1998 | Issued |
Array
(
[id] => 3943120
[patent_doc_number] => 05976903
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-02
[patent_title] => 'Method for manufacturing tunable laser'
[patent_app_type] => 1
[patent_app_number] => 9/020711
[patent_app_country] => US
[patent_app_date] => 1998-02-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[patent_no_of_words] => 1449
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[pdf_file] => patents/05/976/05976903.pdf
[firstpage_image] =>[orig_patent_app_number] => 020711
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/020711 | Method for manufacturing tunable laser | Feb 8, 1998 | Issued |
Array
(
[id] => 4214347
[patent_doc_number] => 06110775
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-08-29
[patent_title] => 'Process for fabrication of a dram cell having a stacked capacitor'
[patent_app_type] => 1
[patent_app_number] => 9/018181
[patent_app_country] => US
[patent_app_date] => 1998-02-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
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[patent_no_of_words] => 13861
[patent_no_of_claims] => 9
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[pdf_file] => patents/06/110/06110775.pdf
[firstpage_image] =>[orig_patent_app_number] => 018181
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/018181 | Process for fabrication of a dram cell having a stacked capacitor | Feb 2, 1998 | Issued |
Array
(
[id] => 4190666
[patent_doc_number] => 06043101
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-03-28
[patent_title] => 'In-situ multiprobe retest method with recovery recognition'
[patent_app_type] => 1
[patent_app_number] => 9/007982
[patent_app_country] => US
[patent_app_date] => 1998-01-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/043/06043101.pdf
[firstpage_image] =>[orig_patent_app_number] => 007982
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/007982 | In-situ multiprobe retest method with recovery recognition | Jan 14, 1998 | Issued |
Array
(
[id] => 4168818
[patent_doc_number] => 06140166
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-10-31
[patent_title] => 'Method for manufacturing semiconductor and method for manufacturing semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 8/997910
[patent_app_country] => US
[patent_app_date] => 1997-12-24
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[pdf_file] => patents/06/140/06140166.pdf
[firstpage_image] =>[orig_patent_app_number] => 997910
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/997910 | Method for manufacturing semiconductor and method for manufacturing semiconductor device | Dec 23, 1997 | Issued |
Array
(
[id] => 4029065
[patent_doc_number] => 05994159
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-30
[patent_title] => 'Self-assemblying micro-mechanical device'
[patent_app_type] => 1
[patent_app_number] => 8/997175
[patent_app_country] => US
[patent_app_date] => 1997-12-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[pdf_file] => patents/05/994/05994159.pdf
[firstpage_image] =>[orig_patent_app_number] => 997175
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/997175 | Self-assemblying micro-mechanical device | Dec 21, 1997 | Issued |
Array
(
[id] => 4069929
[patent_doc_number] => 05970313
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-10-19
[patent_title] => 'Monitoring wafer temperature during thermal processing of wafers by measuring sheet resistance of a test wafer'
[patent_app_type] => 1
[patent_app_number] => 8/994221
[patent_app_country] => US
[patent_app_date] => 1997-12-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_words] => 2723
[patent_no_of_claims] => 15
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/970/05970313.pdf
[firstpage_image] =>[orig_patent_app_number] => 994221
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/994221 | Monitoring wafer temperature during thermal processing of wafers by measuring sheet resistance of a test wafer | Dec 18, 1997 | Issued |
Array
(
[id] => 4038868
[patent_doc_number] => 05942801
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-08-24
[patent_title] => 'Borderless vias with HSQ gap filled metal patterns having high etching resistance'
[patent_app_type] => 1
[patent_app_number] => 8/992430
[patent_app_country] => US
[patent_app_date] => 1997-12-18
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[pdf_file] => patents/05/942/05942801.pdf
[firstpage_image] =>[orig_patent_app_number] => 992430
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/992430 | Borderless vias with HSQ gap filled metal patterns having high etching resistance | Dec 17, 1997 | Issued |
Array
(
[id] => 4196117
[patent_doc_number] => 06130442
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-10-10
[patent_title] => 'Memory chip containing a non-volatile memory register for permanently storing information about the quality of the device and test method therefor'
[patent_app_type] => 1
[patent_app_number] => 8/992607
[patent_app_country] => US
[patent_app_date] => 1997-12-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_words] => 3935
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[pdf_file] => patents/06/130/06130442.pdf
[firstpage_image] =>[orig_patent_app_number] => 992607
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/992607 | Memory chip containing a non-volatile memory register for permanently storing information about the quality of the device and test method therefor | Dec 16, 1997 | Issued |
Array
(
[id] => 4101998
[patent_doc_number] => 06051443
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-04-18
[patent_title] => 'Method for assessing the effects of plasma treatments on wafers of semiconductor material'
[patent_app_type] => 1
[patent_app_number] => 8/990617
[patent_app_country] => US
[patent_app_date] => 1997-12-15
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/051/06051443.pdf
[firstpage_image] =>[orig_patent_app_number] => 990617
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/990617 | Method for assessing the effects of plasma treatments on wafers of semiconductor material | Dec 14, 1997 | Issued |
Array
(
[id] => 4080091
[patent_doc_number] => 05965908
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-10-12
[patent_title] => 'Epitaxial wafer and manufacturing method thereof as well as light-emitting diode with enhanced luminance'
[patent_app_type] => 1
[patent_app_number] => 8/991013
[patent_app_country] => US
[patent_app_date] => 1997-12-15
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[firstpage_image] =>[orig_patent_app_number] => 991013
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/991013 | Epitaxial wafer and manufacturing method thereof as well as light-emitting diode with enhanced luminance | Dec 14, 1997 | Issued |
Array
(
[id] => 4002754
[patent_doc_number] => 05986313
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[patent_issue_date] => 1999-11-16
[patent_title] => 'Semiconductor device comprising MISFETS and method of manufacturing the same'
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[patent_app_number] => 8/988776
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[firstpage_image] =>[orig_patent_app_number] => 988776
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/988776 | Semiconductor device comprising MISFETS and method of manufacturing the same | Dec 10, 1997 | Issued |
Array
(
[id] => 4154810
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[patent_issue_date] => 2000-09-05
[patent_title] => 'Display apparatus using electroluminescence elements and method of manufacturing same'
[patent_app_type] => 1
[patent_app_number] => 8/987460
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[pdf_file] => patents/06/114/06114183.pdf
[firstpage_image] =>[orig_patent_app_number] => 987460
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/987460 | Display apparatus using electroluminescence elements and method of manufacturing same | Dec 8, 1997 | Issued |
Array
(
[id] => 4221835
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[patent_title] => 'Method for improving semiconductor wafer processing'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/985553 | Method for improving semiconductor wafer processing | Dec 4, 1997 | Issued |
Array
(
[id] => 4106178
[patent_doc_number] => 06022750
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-02-08
[patent_title] => 'Method for fabricating semiconductor interconnect having test structures for evaluating electrical characteristics of the interconnect'
[patent_app_type] => 1
[patent_app_number] => 8/984247
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/984247 | Method for fabricating semiconductor interconnect having test structures for evaluating electrical characteristics of the interconnect | Dec 2, 1997 | Issued |
Array
(
[id] => 3967110
[patent_doc_number] => 05956596
[patent_country] => US
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[patent_issue_date] => 1999-09-21
[patent_title] => 'Method of forming and cleaning a laser marking region at a round zone of a semiconductor wafer'
[patent_app_type] => 1
[patent_app_number] => 8/980912
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/980912 | Method of forming and cleaning a laser marking region at a round zone of a semiconductor wafer | Nov 30, 1997 | Issued |
Array
(
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[patent_title] => 'Method of making a semiconductor device having an SOI structure'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/979621 | Method of making a semiconductor device having an SOI structure | Nov 27, 1997 | Issued |
Array
(
[id] => 4070299
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[patent_title] => 'Method of manufacturing transistor array'
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[firstpage_image] =>[orig_patent_app_number] => 980083
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/980083 | Method of manufacturing transistor array | Nov 25, 1997 | Issued |
Array
(
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[pdf_file] => patents/06/087/06087190.pdf
[firstpage_image] =>[orig_patent_app_number] => 973582
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/973582 | Automatic test process with non-volatile result table store | Nov 16, 1997 | Issued |