Andrew J Oyer

Array ( [id] => 4016363 [patent_doc_number] => 05923977 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-13 [patent_title] => 'Method of forming CMOS circuitry including patterning a layer of conductive material overlying field isolation oxide' [patent_app_type] => 1 [patent_app_number] => 8/970347 [patent_app_country] => US [patent_app_date] => 1997-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 22 [patent_no_of_words] => 3048 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/923/05923977.pdf [firstpage_image] =>[orig_patent_app_number] => 970347 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4190980 [patent_doc_number] => 06130109 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-10 [patent_title] => 'Microbridge structure and method for forming a microstructure suspended by a micro support' [patent_app_type] => 1 [patent_app_number] => 8/966311 [patent_app_country] => US [patent_app_date] => 1997-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3558 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 290 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/130/06130109.pdf [firstpage_image] =>[orig_patent_app_number] => 966311 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4069892 [patent_doc_number] => 05933738 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-03 [patent_title] => 'Method of forming a field effect transistor' [patent_app_type] => 1 [patent_app_number] => 8/964779 [patent_app_country] => US [patent_app_date] => 1997-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 2762 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/933/05933738.pdf [firstpage_image] =>[orig_patent_app_number] => 964779 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4069879 [patent_doc_number] => 05970311 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-19 [patent_title] => 'Method and structure for optimizing the performance of a semiconductor device having dense transistors' [patent_app_type] => 1 [patent_app_number] => 8/961980 [patent_app_country] => US [patent_app_date] => 1997-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4513 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/970/05970311.pdf [firstpage_image] =>[orig_patent_app_number] => 961980 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4197278 [patent_doc_number] => 06043523 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-28 [patent_title] => 'Charge coupled device and method of fabricating the same' [patent_app_type] => 1 [patent_app_number] => 8/960213 [patent_app_country] => US [patent_app_date] => 1997-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 2769 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/043/06043523.pdf [firstpage_image] =>[orig_patent_app_number] => 960213 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4002313 [patent_doc_number] => 05986282 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-16 [patent_title] => 'Method of measuring electrical characteristics of semiconductor circuit in wafer state and semiconductor device for the same' [patent_app_type] => 1 [patent_app_number] => 8/957157 [patent_app_country] => US [patent_app_date] => 1997-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4281 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/986/05986282.pdf [firstpage_image] =>[orig_patent_app_number] => 957157 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4106822 [patent_doc_number] => 06022793 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-08 [patent_title] => 'Silicon and oxygen ion co-implantation for metallic gettering in epitaxial wafers' [patent_app_type] => 1 [patent_app_number] => 8/954960 [patent_app_country] => US [patent_app_date] => 1997-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4134 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/022/06022793.pdf [firstpage_image] =>[orig_patent_app_number] => 954960 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4031136 [patent_doc_number] => 05963817 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-05 [patent_title] => 'Bulk and strained silicon on insulator using local selective oxidation' [patent_app_type] => 1 [patent_app_number] => 8/951827 [patent_app_country] => US [patent_app_date] => 1997-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 2840 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/963/05963817.pdf [firstpage_image] =>[orig_patent_app_number] => 951827 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3966697 [patent_doc_number] => 05956567 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-21 [patent_title] => 'Semiconductor chip and semiconductor wafer having power supply pads for probe test' [patent_app_type] => 1 [patent_app_number] => 8/949587 [patent_app_country] => US [patent_app_date] => 1997-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 7263 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/956/05956567.pdf [firstpage_image] =>[orig_patent_app_number] => 949587 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4063466 [patent_doc_number] => 06008061 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-28 [patent_title] => 'Method of manufacturing semiconductor device having a test pad' [patent_app_type] => 1 [patent_app_number] => 8/948481 [patent_app_country] => US [patent_app_date] => 1997-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 19 [patent_no_of_words] => 2263 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/008/06008061.pdf [firstpage_image] =>[orig_patent_app_number] => 948481 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4129575 [patent_doc_number] => 06033923 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-07 [patent_title] => 'Methods of evaluating titanium nitride and of forming tungsten wiring' [patent_app_type] => 1 [patent_app_number] => 8/946777 [patent_app_country] => US [patent_app_date] => 1997-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3529 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/033/06033923.pdf [firstpage_image] =>[orig_patent_app_number] => 946777 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3941801 [patent_doc_number] => 05946545 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-31 [patent_title] => 'Semiconductor stack structures and fabrication/sparing methods utilizing programmable spare circuit' [patent_app_type] => 1 [patent_app_number] => 8/942515 [patent_app_country] => US [patent_app_date] => 1997-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 6674 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/946/05946545.pdf [firstpage_image] =>[orig_patent_app_number] => 942515 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4153695 [patent_doc_number] => 06103542 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-15 [patent_title] => 'Method of manufacturing an optoelectronic semiconductor device comprising a mesa' [patent_app_type] => 1 [patent_app_number] => 8/937433 [patent_app_country] => US [patent_app_date] => 1997-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 4115 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/103/06103542.pdf [firstpage_image] =>[orig_patent_app_number] => 937433 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3934575 [patent_doc_number] => 05972730 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-26 [patent_title] => 'Nitride based compound semiconductor light emitting device and method for producing the same' [patent_app_type] => 1 [patent_app_number] => 8/937160 [patent_app_country] => US [patent_app_date] => 1997-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 22 [patent_no_of_words] => 9012 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/972/05972730.pdf [firstpage_image] =>[orig_patent_app_number] => 937160 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4016163 [patent_doc_number] => 05923963 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-13 [patent_title] => 'Method of manufacturing a semiconductor display device' [patent_app_type] => 1 [patent_app_number] => 8/936703 [patent_app_country] => US [patent_app_date] => 1997-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 33 [patent_no_of_words] => 10652 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/923/05923963.pdf [firstpage_image] =>[orig_patent_app_number] => 936703 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3936905 [patent_doc_number] => 05981309 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-09 [patent_title] => 'Method for fabricating charge coupled device image sensor' [patent_app_type] => 1 [patent_app_number] => 8/934769 [patent_app_country] => US [patent_app_date] => 1997-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 2280 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/981/05981309.pdf [firstpage_image] =>[orig_patent_app_number] => 934769 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3941196 [patent_doc_number] => 05989933 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-23 [patent_title] => 'Method of forming a cadmium telluride/silicon structure' [patent_app_type] => 1 [patent_app_number] => 8/932095 [patent_app_country] => US [patent_app_date] => 1997-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 7 [patent_no_of_words] => 3048 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/989/05989933.pdf [firstpage_image] =>[orig_patent_app_number] => 932095 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4132321 [patent_doc_number] => 06127702 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-03 [patent_title] => 'Semiconductor device having an SOI structure and manufacturing method therefor' [patent_app_type] => 1 [patent_app_number] => 8/931697 [patent_app_country] => US [patent_app_date] => 1997-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 55 [patent_no_of_words] => 17668 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 18 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/127/06127702.pdf [firstpage_image] =>[orig_patent_app_number] => 931697 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4029023 [patent_doc_number] => 05994156 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-30 [patent_title] => 'Method of making gate and source lines in TFT LCD panels using pure aluminum metal' [patent_app_type] => 1 [patent_app_number] => 8/928600 [patent_app_country] => US [patent_app_date] => 1997-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 5476 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/994/05994156.pdf [firstpage_image] =>[orig_patent_app_number] => 928600 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4238941 [patent_doc_number] => 06118137 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-12 [patent_title] => 'Test structure responsive to electrical signals for determining lithographic misalignment of conductors relative to vias' [patent_app_type] => 1 [patent_app_number] => 8/925383 [patent_app_country] => US [patent_app_date] => 1997-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 3640 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/118/06118137.pdf [firstpage_image] =>[orig_patent_app_number] => 925383 [rel_patent_id] =>[rel_patent_doc_number] =>)