Search

Andrew J Oyer

Examiner (ID: 2471, Phone: (571)270-0347 , Office: P/1767 )

Most Active Art Unit
1767
Art Unit(s)
1767
Total Applications
638
Issued Applications
430
Pending Applications
78
Abandoned Applications
130

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4057527 [patent_doc_number] => 05895267 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-20 [patent_title] => 'Method to obtain a low resistivity and conformity chemical vapor deposition titanium film' [patent_app_type] => 1 [patent_app_number] => 8/889839 [patent_app_country] => US [patent_app_date] => 1997-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 4005 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/895/05895267.pdf [firstpage_image] =>[orig_patent_app_number] => 889839 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/889839
Method to obtain a low resistivity and conformity chemical vapor deposition titanium film Jul 8, 1997 Issued
Array ( [id] => 3936893 [patent_doc_number] => 05981308 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-09 [patent_title] => 'Method for manufacturing minute silicon mechanical device' [patent_app_type] => 1 [patent_app_number] => 8/887927 [patent_app_country] => US [patent_app_date] => 1997-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2525 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/981/05981308.pdf [firstpage_image] =>[orig_patent_app_number] => 887927 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/887927
Method for manufacturing minute silicon mechanical device Jul 2, 1997 Issued
Array ( [id] => 3805845 [patent_doc_number] => 05854088 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-29 [patent_title] => 'Method of manufacturing a surface-emitting laser' [patent_app_type] => 1 [patent_app_number] => 8/885843 [patent_app_country] => US [patent_app_date] => 1997-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 2192 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/854/05854088.pdf [firstpage_image] =>[orig_patent_app_number] => 885843 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/885843
Method of manufacturing a surface-emitting laser Jun 29, 1997 Issued
Array ( [id] => 3943781 [patent_doc_number] => 05998235 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-07 [patent_title] => 'Method of fabrication for mercury-based quaternary alloys of infrared sensitive materials' [patent_app_type] => 1 [patent_app_number] => 8/882881 [patent_app_country] => US [patent_app_date] => 1997-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 3321 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/998/05998235.pdf [firstpage_image] =>[orig_patent_app_number] => 882881 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/882881
Method of fabrication for mercury-based quaternary alloys of infrared sensitive materials Jun 25, 1997 Issued
Array ( [id] => 4023983 [patent_doc_number] => 05882979 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-16 [patent_title] => 'Method for forming controllable surface enhanced three dimensional objects' [patent_app_type] => 1 [patent_app_number] => 8/881928 [patent_app_country] => US [patent_app_date] => 1997-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 2210 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/882/05882979.pdf [firstpage_image] =>[orig_patent_app_number] => 881928 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/881928
Method for forming controllable surface enhanced three dimensional objects Jun 24, 1997 Issued
Array ( [id] => 3964470 [patent_doc_number] => 05885846 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-23 [patent_title] => 'Method and apparatus for testing of dielectric defects in a packaged semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/879833 [patent_app_country] => US [patent_app_date] => 1997-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 7270 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/885/05885846.pdf [firstpage_image] =>[orig_patent_app_number] => 879833 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/879833
Method and apparatus for testing of dielectric defects in a packaged semiconductor memory device Jun 18, 1997 Issued
Array ( [id] => 3791205 [patent_doc_number] => 05780316 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-14 [patent_title] => 'Linewidth control apparatus and method' [patent_app_type] => 1 [patent_app_number] => 8/879109 [patent_app_country] => US [patent_app_date] => 1997-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1445 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/780/05780316.pdf [firstpage_image] =>[orig_patent_app_number] => 879109 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/879109
Linewidth control apparatus and method Jun 18, 1997 Issued
Array ( [id] => 3964652 [patent_doc_number] => 05885860 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-23 [patent_title] => 'Silicon carbide transistor and method' [patent_app_type] => 1 [patent_app_number] => 8/874433 [patent_app_country] => US [patent_app_date] => 1997-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2298 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/885/05885860.pdf [firstpage_image] =>[orig_patent_app_number] => 874433 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/874433
Silicon carbide transistor and method Jun 15, 1997 Issued
Array ( [id] => 3947264 [patent_doc_number] => 05981995 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-09 [patent_title] => 'Static random access memory cell having buried sidewall transistors, buried bit lines, and buried vdd and vss nodes' [patent_app_type] => 1 [patent_app_number] => 8/874877 [patent_app_country] => US [patent_app_date] => 1997-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4308 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/981/05981995.pdf [firstpage_image] =>[orig_patent_app_number] => 874877 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/874877
Static random access memory cell having buried sidewall transistors, buried bit lines, and buried vdd and vss nodes Jun 12, 1997 Issued
Array ( [id] => 3968481 [patent_doc_number] => 05904495 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-18 [patent_title] => 'Interconnection technique for hybrid integrated devices' [patent_app_type] => 1 [patent_app_number] => 8/873123 [patent_app_country] => US [patent_app_date] => 1997-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 1668 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/904/05904495.pdf [firstpage_image] =>[orig_patent_app_number] => 873123 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/873123
Interconnection technique for hybrid integrated devices Jun 10, 1997 Issued
Array ( [id] => 4185398 [patent_doc_number] => 06093592 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-25 [patent_title] => 'Method of manufacturing a semiconductor apparatus having a silicon-on-insulator structure' [patent_app_type] => 1 [patent_app_number] => 8/872335 [patent_app_country] => US [patent_app_date] => 1997-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 31 [patent_no_of_words] => 6807 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/093/06093592.pdf [firstpage_image] =>[orig_patent_app_number] => 872335 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/872335
Method of manufacturing a semiconductor apparatus having a silicon-on-insulator structure Jun 9, 1997 Issued
Array ( [id] => 4023671 [patent_doc_number] => 05882957 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-16 [patent_title] => 'Ball grid array packaging method for an integrated circuit and structure realized by the method' [patent_app_type] => 1 [patent_app_number] => 8/871471 [patent_app_country] => US [patent_app_date] => 1997-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 16 [patent_no_of_words] => 1792 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/882/05882957.pdf [firstpage_image] =>[orig_patent_app_number] => 871471 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/871471
Ball grid array packaging method for an integrated circuit and structure realized by the method Jun 8, 1997 Issued
Array ( [id] => 4243577 [patent_doc_number] => 06091086 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-18 [patent_title] => 'Reverse blocking IGBT' [patent_app_type] => 1 [patent_app_number] => 8/870507 [patent_app_country] => US [patent_app_date] => 1997-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 3841 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/091/06091086.pdf [firstpage_image] =>[orig_patent_app_number] => 870507 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/870507
Reverse blocking IGBT Jun 5, 1997 Issued
Array ( [id] => 4006330 [patent_doc_number] => 05888840 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-30 [patent_title] => 'Process of growing multiple quantum well structure for adjusting photoluminescence peak wavelengths to target value' [patent_app_type] => 1 [patent_app_number] => 8/869443 [patent_app_country] => US [patent_app_date] => 1997-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 18 [patent_no_of_words] => 4847 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/888/05888840.pdf [firstpage_image] =>[orig_patent_app_number] => 869443 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/869443
Process of growing multiple quantum well structure for adjusting photoluminescence peak wavelengths to target value Jun 4, 1997 Issued
Array ( [id] => 4027112 [patent_doc_number] => 05925919 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-20 [patent_title] => 'CMOS Semiconductor structure and process for producing the same' [patent_app_type] => 1 [patent_app_number] => 8/869101 [patent_app_country] => US [patent_app_date] => 1997-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 1681 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/925/05925919.pdf [firstpage_image] =>[orig_patent_app_number] => 869101 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/869101
CMOS Semiconductor structure and process for producing the same Jun 3, 1997 Issued
Array ( [id] => 4004115 [patent_doc_number] => 05960277 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-28 [patent_title] => 'Method of making a merged device with aligned trench FET and buried emitter patterns' [patent_app_type] => 1 [patent_app_number] => 8/868525 [patent_app_country] => US [patent_app_date] => 1997-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1865 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/960/05960277.pdf [firstpage_image] =>[orig_patent_app_number] => 868525 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/868525
Method of making a merged device with aligned trench FET and buried emitter patterns Jun 3, 1997 Issued
Array ( [id] => 3774173 [patent_doc_number] => 05817570 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-06 [patent_title] => 'Semiconductor structure for an MOS transistor and method for fabricating the semiconductor structure' [patent_app_type] => 1 [patent_app_number] => 8/870121 [patent_app_country] => US [patent_app_date] => 1997-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 2482 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/817/05817570.pdf [firstpage_image] =>[orig_patent_app_number] => 870121 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/870121
Semiconductor structure for an MOS transistor and method for fabricating the semiconductor structure Jun 2, 1997 Issued
Array ( [id] => 4221962 [patent_doc_number] => 06111269 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-29 [patent_title] => 'Circuit, structure and method of testing a semiconductor, such as an integrated circuit' [patent_app_type] => 1 [patent_app_number] => 8/865667 [patent_app_country] => US [patent_app_date] => 1997-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 5173 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/111/06111269.pdf [firstpage_image] =>[orig_patent_app_number] => 865667 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/865667
Circuit, structure and method of testing a semiconductor, such as an integrated circuit May 29, 1997 Issued
Array ( [id] => 4131560 [patent_doc_number] => 06121119 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-19 [patent_title] => 'Resistor fabrication' [patent_app_type] => 1 [patent_app_number] => 8/865357 [patent_app_country] => US [patent_app_date] => 1997-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 16 [patent_no_of_words] => 5840 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/121/06121119.pdf [firstpage_image] =>[orig_patent_app_number] => 865357 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/865357
Resistor fabrication May 28, 1997 Issued
Array ( [id] => 4038626 [patent_doc_number] => 05926690 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-20 [patent_title] => 'Run-to-run control process for controlling critical dimensions' [patent_app_type] => 1 [patent_app_number] => 8/864489 [patent_app_country] => US [patent_app_date] => 1997-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3650 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/926/05926690.pdf [firstpage_image] =>[orig_patent_app_number] => 864489 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/864489
Run-to-run control process for controlling critical dimensions May 27, 1997 Issued
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