Andrew J Oyer

Array ( [id] => 1280741 [patent_doc_number] => 06642064 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-04 [patent_title] => 'Method of making a high density programmable logic device in a multichip module package' [patent_app_type] => B1 [patent_app_number] => 08/810567 [patent_app_country] => US [patent_app_date] => 1997-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3603 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/642/06642064.pdf [firstpage_image] =>[orig_patent_app_number] => 08810567 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4003034 [patent_doc_number] => 06004866 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-21 [patent_title] => 'Method for manufacturing bonded wafer and bonded wafer manufactured thereby' [patent_app_type] => 1 [patent_app_number] => 8/808655 [patent_app_country] => US [patent_app_date] => 1997-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 6915 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/004/06004866.pdf [firstpage_image] =>[orig_patent_app_number] => 808655 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3836846 [patent_doc_number] => 05846878 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-08 [patent_title] => 'Method of manufacturing a wiring layer in a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/808529 [patent_app_country] => US [patent_app_date] => 1997-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 3574 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/846/05846878.pdf [firstpage_image] =>[orig_patent_app_number] => 808529 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3824240 [patent_doc_number] => 05731214 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-24 [patent_title] => 'Manufacture of semiconductor device with self-aligned doping' [patent_app_type] => 1 [patent_app_number] => 8/808241 [patent_app_country] => US [patent_app_date] => 1997-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 23 [patent_no_of_words] => 4243 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/731/05731214.pdf [firstpage_image] =>[orig_patent_app_number] => 808241 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4055878 [patent_doc_number] => 05969381 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-19 [patent_title] => 'Semiconductor device with unbreakable testing elements for evaluating components and process of fabrication thereof' [patent_app_type] => 1 [patent_app_number] => 8/805973 [patent_app_country] => US [patent_app_date] => 1997-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 44 [patent_no_of_words] => 13406 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/969/05969381.pdf [firstpage_image] =>[orig_patent_app_number] => 805973 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3925712 [patent_doc_number] => 05877036 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-02 [patent_title] => 'Overlay measuring method using correlation function' [patent_app_type] => 1 [patent_app_number] => 8/806983 [patent_app_country] => US [patent_app_date] => 1997-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 25 [patent_no_of_words] => 4210 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/877/05877036.pdf [firstpage_image] =>[orig_patent_app_number] => 806983 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3892266 [patent_doc_number] => 05894161 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-13 [patent_title] => 'Interconnect with pressure sensing mechanism for testing semiconductor wafers' [patent_app_type] => 1 [patent_app_number] => 8/805126 [patent_app_country] => US [patent_app_date] => 1997-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 17 [patent_no_of_words] => 5802 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/894/05894161.pdf [firstpage_image] =>[orig_patent_app_number] => 805126 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3890858 [patent_doc_number] => 05894065 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-13 [patent_title] => 'Method for improving the intermediate dielectric profile, particularly for non-volatile memories' [patent_app_type] => 1 [patent_app_number] => 8/802619 [patent_app_country] => US [patent_app_date] => 1997-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 14 [patent_no_of_words] => 3452 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/894/05894065.pdf [firstpage_image] =>[orig_patent_app_number] => 802619 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3966954 [patent_doc_number] => 05956585 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-21 [patent_title] => 'Method of forming a self-aligned damage-free buried contact' [patent_app_type] => 1 [patent_app_number] => 8/803035 [patent_app_country] => US [patent_app_date] => 1997-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 1104 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 17 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/956/05956585.pdf [firstpage_image] =>[orig_patent_app_number] => 803035 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3858461 [patent_doc_number] => 05792674 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-11 [patent_title] => 'Method of making a tapered thickness waveguide intergrated semiconductor laser' [patent_app_type] => 1 [patent_app_number] => 8/799931 [patent_app_country] => US [patent_app_date] => 1997-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2468 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 293 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/792/05792674.pdf [firstpage_image] =>[orig_patent_app_number] => 799931 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3836394 [patent_doc_number] => 05846848 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-08 [patent_title] => 'Polysilicon electromigration sensor which can detect and monitor electromigration in composite metal lines on integrated circuit structures with improved sensitivity' [patent_app_type] => 1 [patent_app_number] => 8/796351 [patent_app_country] => US [patent_app_date] => 1997-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 3034 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/846/05846848.pdf [firstpage_image] =>[orig_patent_app_number] => 796351 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4113670 [patent_doc_number] => 06046069 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-04 [patent_title] => 'Solid-state image pick-up device and method for manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 8/796887 [patent_app_country] => US [patent_app_date] => 1997-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 42 [patent_no_of_words] => 13613 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/046/06046069.pdf [firstpage_image] =>[orig_patent_app_number] => 796887 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4019563 [patent_doc_number] => 05880482 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-09 [patent_title] => 'Low dark current photodetector' [patent_app_type] => 1 [patent_app_number] => 8/790653 [patent_app_country] => US [patent_app_date] => 1997-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 27 [patent_no_of_words] => 3752 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/880/05880482.pdf [firstpage_image] =>[orig_patent_app_number] => 790653 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4029238 [patent_doc_number] => 05994171 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-30 [patent_title] => 'Method of making lateral components in power semiconductor devices' [patent_app_type] => 1 [patent_app_number] => 8/787741 [patent_app_country] => US [patent_app_date] => 1997-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 2440 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/994/05994171.pdf [firstpage_image] =>[orig_patent_app_number] => 787741 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3867842 [patent_doc_number] => 05837601 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-17 [patent_title] => 'CMOS semiconductor device having dual-gate electrode construction and method of production of the same' [patent_app_type] => 1 [patent_app_number] => 8/788191 [patent_app_country] => US [patent_app_date] => 1997-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 5149 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/837/05837601.pdf [firstpage_image] =>[orig_patent_app_number] => 788191 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3825621 [patent_doc_number] => 05783472 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-21 [patent_title] => 'Method of making an SOI transistor' [patent_app_type] => 1 [patent_app_number] => 8/787797 [patent_app_country] => US [patent_app_date] => 1997-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 55 [patent_no_of_words] => 9641 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/783/05783472.pdf [firstpage_image] =>[orig_patent_app_number] => 787797 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3740635 [patent_doc_number] => 05786258 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-28 [patent_title] => 'Method of making an SOI transistor' [patent_app_type] => 1 [patent_app_number] => 8/786879 [patent_app_country] => US [patent_app_date] => 1997-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 55 [patent_no_of_words] => 9634 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/786/05786258.pdf [firstpage_image] =>[orig_patent_app_number] => 786879 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3838935 [patent_doc_number] => 05744398 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-28 [patent_title] => 'Method of forming electrode of semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/788107 [patent_app_country] => US [patent_app_date] => 1997-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 2162 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/744/05744398.pdf [firstpage_image] =>[orig_patent_app_number] => 788107 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4291679 [patent_doc_number] => 06180439 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-30 [patent_title] => 'Method for fabricating a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/784290 [patent_app_country] => US [patent_app_date] => 1997-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 34 [patent_no_of_words] => 11046 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 16 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/180/06180439.pdf [firstpage_image] =>[orig_patent_app_number] => 784290 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3759334 [patent_doc_number] => 05843799 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-01 [patent_title] => 'Circuit module redundancy architecture process' [patent_app_type] => 1 [patent_app_number] => 8/782135 [patent_app_country] => US [patent_app_date] => 1997-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 30 [patent_no_of_words] => 8471 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/843/05843799.pdf [firstpage_image] =>[orig_patent_app_number] => 782135 [rel_patent_id] =>[rel_patent_doc_number] =>)